• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.347-350
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• 2001

A typical Mold method is to form a gate electrode, a gate oxide, and emitter tip after fabrication of mold shape using wet-etching of Si substrate. In this study, however, new Mold method using a side wall space structure is used in order to make sharper emitter tip with a gate electrode. Using LPCVD(low pressure chemical vapor deposition), a gate oxide and electrode layer are formed on a Si substrate, and then BPSG(Boro phospher silicate glass) thin film is deposited. After, the BPSG thin film is flowed into a mold as high temperature in order to form a sharp mold structure. Next TiN thin film is deposited as a emitter tip substance. The unfinished device with a glass substrate is bonded by anodic bonding techniques to transfer the emitters to a glass substrate, and Si substrate is etched using KOH-deionized water solution. Finally, we made sharp field emitter array with gate electrode on the glass substrate.

• 전기전자학회논문지
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• 제21권2호
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• pp.170-173
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• 2017

본 연구에서는 Al, Mo 및 Pt 금속 물질을 a-IGZO 박막트랜지스터의 게이트 전극으로 플라스틱 기판 위에 형성하여 제작하고, 게이트 물질에 따른 전기적 특성을 측정하였다. Al 게이트 전극에 비해 Pt 게이트 전극을 사용한 박막트랜지스터의 문턱전압은 -4.1V에서 -0.3 V까지 감소하였고, 전하이동도는 $15.8cm^2/V{\cdot}s$에서 $22.1cm^2/V{\cdot}s$ 로 향상되었다. 게이트 전극에 따른 박막트랜지스터의 문턱전압 이동은 전극의 일함수와 채널층의 페르미 에너지 차이로 인한 영향이라는 것을 확인 할 수 있었다. 또한, 채널 물질의 페르미 에너지를 고려하였을 경우에 Pt 게이트 전극이 박막트랜지스터의 전기적 특성 면에서 적합한 물질로 확인되었다. 추가적으로 Mo 게이트 전극을 사용한 박막트랜지스터에 대한 특성도 본 논문에서 다룬다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.889-892
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• 2009

We have developed a practical printing technology for the gate electrode of organic thin film transistors(OTFTs) by combining screen-printing with wet-etching process using nano-silver ink as a conducting material. The screen-printed and wet-etched Ag electrode exhibited a minimum line width of ~5 um, the thickness of ~65 nm, and a resistivity of ${\sim}10^{-6}{\Omega}{\cdot}cm$, producing good geometrical and electrical characteristics for gate electrode. The OTFTs with the screen-printed and wet-etched Ag electrode produced the saturation mobility of $0.13cm^2$/Vs and current on/off ratio of $1.79{\times}10^6$, being comparable to those of OTFT with the thermally evaporated Al gate electrode.

• 한국전기전자재료학회논문지
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• 제18권2호
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• pp.120-124
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• 2005

In this work, MOS capacitors were used to study the electrical properties of Mo gate electrode deposited on ZrO$_2$. The workfunctions of Mo gate extracted from C-V curves were appropriate for PMOS. Thermal stability of Mo metal was investigated by analyzing the variations of workfunction and EOT(effective oxide thickness) after 600, 700, and 800 $^{\circ}C$ RTA(rapid thermal annealing). It was found that Mo gate was stable up to 800 $^{\circ}C$ with underlying ZrO$_2$. The resistivities of Mo were 35$\mu$Ω$.$cm∼ 75$\mu$Ω$.$cm. These values are lower than those of heavily doped polysilicon. Based on these measurements, it can be concluded that Mo metal gate with ZrO$_2$ gate insulator is an excellent gate material for PMOS.

• 한국전기전자재료학회논문지
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• 제17권3호
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• pp.259-266
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• 2004

In this paper. a new two types of EST(Emitter Switched Thyristor) structures are proposed to improve the electrical characteristics including the current saturation capability. Besides, the two dimensional numerical simulations were carried out using MEDICI to verify the validity of the device and examine the electrical characteristics. First, a vortical trench electrode EST device is proposed to improve snap-back effect and its blocking voltage. Second, a dual trench gate EST device is proposed to obtain high voltage current saturation characteristics and high blocking voltage and to eliminate snap-back effect. The two proposed devices have superior electrical characteristics when compared to conventional devices. In the vertical trench electrode EST, the snap-back effect is considerably improved by using the vertical trench gate and cathode electrode and the blocking voltage is one times better than that of the conventional EST. And in the dual trench gate EST, the snap-back effect is completely removed by using the series turn-on and turn-off MOSFET and the blocking voltage is one times better than that of the conventional EST. Especially current saturation capability is three times better than that of the other EST.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Progress in Superconductivity
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• 제3권1호
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• pp.74-77
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• 2001

We have fabricated a high-Tc superconductive transistor with polyvinylidene fluoride (PVDF) gate electrode on MgO bicrystal Josephson junction by spin-coating method. The PVDF ferroelectric film is found to be suitable fur a gate electrode of the superconductive transistor since it has not only small leakage current but also high dieletric constant at low temperature. For the application of superconducting-FET, we investigated millimeter wave properties (60 GHz band) of the Josephson junction with PVDF gate electrode.

• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.912-917
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• 2006

In this paper, Trench emitter electrode IGBT structure is proposed and studied numerically using the device simulator, MEDICI. The breakdown voltage, on-state voltage drop, latch up current density and turn-off time of the proposed structure are compared with those of the conventional trench gate IGBT(TIGBT) structures. Enhancement of the breakdown voltage by 19 % is obtained in the proposed structure due to dispersion of electric field at the edge of the bottom trench gate by trench emitter electrode. In addition, the on-state voltage drop and the latch up current density are improved by 25 %, 16 % respectively. However increase of turn-off time in proposed structures are negligible.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.163-166
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• 2002

We investigated structural and electrical properties of Metal-Oxide-Semiconductor(MOS) structure using Hafnium $oxide(HfO_{2})$ as high-k gate dielectric material. $HfO_{2}$ films are ultrathin gate dielectric material witch have a thickness less than 2.0nm， so it is spotlighted to be substituted $SiO_{2}$ as gate dielectric material. In this paper We have grown $HfO_{2}$ films with pt electrode on P-type Silicon substrate by RF magnetron sputtering system using $HfO_{2}$ target and oserved the property of semiconductor-oxide interface. Using pt electrode, it is necessary to be annealed at ${300^{\circ}C}$. This process is to increase an adhesion ratio between $HfO_{2}$ films with pt electrode. In film deposition process, the deposition time of $HfO_{2}$ films is an important parameter. Structura1 properties are invetigated by AES depth profile, and electrical properties by Capacitance-Voltage characteristic. Interface trap density are measured to observe the interface between $HfO_{2}$ with Si using High-frequency(1MHz) C-V and Quasi - static C-V characteristic.

• 한국전기전자재료학회논문지
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• 제19권9호
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• pp.808-812
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• 2006

In this dissertation, Ru-Zr metal gate electrode deposited on two kinds of dielectric were formed for MOS capacitor. Sample co-sputtering method was used as a alloy deposition method. Various atomic composition was achieved when metal film was deposited by controlling sputtering power. To study the characteristics of metal gate electrode, C-V(capacitance-voltage) and I-V(current-voltage) measurements were performed. Work function and equivalent oxide thickness were extracted from C-V curves by using NCSU(North Carolina State University) quantum model. After the annealing at various temperature, thermal/chemical stability was verified by measuring the variation of effective oxide thickness and work function. This dissertation verified that Ru-Zr gate electrodes deposited on $SiO_{2}\;and\;ZrO_{2}$ have compatible work functions for NMOS at the specified atomic composition and this metal alloys are thermally stable. Ru-Zr metal gate electrode deposited on $SiO_{2}\;and\;ZrO_{2}$ exhibit low sheet resistance and this values were varied with temperature. Metal alloy deposited on two kinds of dielectric proposed in this dissertation will be used in company with high-k dielectric replacing polysilicon and will lead improvement of CMOS properties.