• 제목/요약/키워드: field-effect transistor

검색결과 794건 처리시간 0.031초

Ambipolarity Factor of Tunneling Field-Effect Transistors (TFETs)

  • Jang, Jung-Shik;Choi, Woo-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제11권4호
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    • pp.272-277
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    • 2011
  • The ambipolar behavior of tunneling field-effect transistors (TFETs) has been investigated quantitatively by introducing a novel parameter: ambipolarity factor (${\nu}$). It has been found that the malfunction of TFET can result from the ambipolar state which is not on- or off- state. Therefore, the effect of ambipolar behavior on the device performance should be parameterized quantitatively, and this has been successfully evaluated as a function of device structure, gate oxide thickness, supply voltage, drain doping concentration and body doping concentration by using ${\nu}$.

Spin Transport in a Ferromagnet/Semiconductor/Ferromagnet Structure: a Spin Transistor

  • Lee, W.Y;Bland, J.A.C
    • Journal of Magnetics
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    • 제7권1호
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    • pp.4-8
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    • 2002
  • The magnetoresistance (MR) and the magnetization reversal of a lateral spin-injection device based on a spin-polarized field effect transistor (spin FET) have been investigated. The device consists of a two-dimensional electron gas (2DEG) system in an InAs single quantum well (SQW) and two ferromagnetic $(Ni_{80}Fe_{20})$ contacts: all injector (source) and a detector (drain). Spin-polarized electrons are injected from the first contact and, after propagating through the InAs SQW are collected by the second contact. By engineering the shape of the permalloy contacts, we were able to observe distinct switching fields $(H_c)$ from the injector and the collector by using scanning Kerr microscopy and MR measurements. Magneto-optic Kerr effect (MOKE) hysteresis loops demonstrate that there is a range of magnetic field (20~60 Oe), at room temperature, over which the magnetization in one contact is aligned antiparallel to that in the other. The MOKE results are consistent with the variation of the magnetoresistance in the spin-injection device.

High-Speed Low-Power Junctionless Field-Effect Transistor with Ultra-Thin Poly-Si Channel for Sub-10-nm Technology Node

  • Kim, Youngmin;Lee, Junsoo;Cho, Yongbeom;Lee, Won Jae;Cho, Seongjae
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권2호
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    • pp.159-165
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    • 2016
  • Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

Si1-xGex Positive Feedback Field-effect Transistor with Steep Subthreshold Swing for Low-voltage Operation

  • Hwang, Sungmin;Kim, Hyungjin;Kwon, Dae Woong;Lee, Jong-Ho;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권2호
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    • pp.216-222
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    • 2017
  • The most prominent challenge for MOSFET scaling is to reduce power consumption; however, the supply voltage ($V_{DD}$) cannot be scaled down because of the carrier injection mechanism. To overcome this limit, a new type of field-effect transistor using positive feedback as a carrier injection mechanism (FBFET) has been proposed. In this study we have investigated the electrical characteristics of a $Si_{1-x}Ge_x$ FBFET with one gate and one-sided $Si_3N_4$ spacer using TCAD simulations. To reduce the drain bias dependency, $Si_{1-x}Ge_x$ was introduced as a low-bandgap material, and the minimum subthreshold swing was obtained as 2.87 mV/dec. This result suggests that a $Si_{1-x}Ge_x$ FBFET is a promising candidate for future low-power devices.

FET센서 감도 향상 측정을 위한 최적화 (Optimization for Higher Sensitive Measurements of FET-type Sensors)

  • 손영수
    • 공업화학
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    • 제26권1호
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    • pp.116-119
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    • 2015
  • 전계 효과 트랜지스터(FET) 기반의 이온 또는 바이오센서에 대한 연구는 지금까지 활발하게 이루어지고 있다. 본 논문에서는 여러 가지 측정 방법 중에 FET 게이트 절연체 위의 감지막과 이온 또는 생분자의 상호작용으로 전하 분포의 변화가 일어나면 이로 인해 드레인 전류의 변화를 측정하는 방법을 기반으로, 동일한 입력 신호, 즉 동일한 이온 또는 생분자의 농도에 대해 최적의 출력 신호를 얻기 위한 방법에 대해 논의한다. 대표적인 FET 센서는 이온 감지 FET (ISFET)로 본 논문에서는 pH를 측정하는 센서를 이용하였다. ISFET는 게이트 전압 대신 기준전극 전압을 가하는데 이 기준전극 전압과 드레인 전류의 관계식을 측정하여, 가장 기울기가 큰 곳을 찾아 이를 기준으로 동작범위에서의 입력 변화에 대해 출력 신호인 포화영역에서 드레인 전류의 변화가 큰 조건을 설정해 보았다.

Gate Overlap에 따른 나노선 CMOS Inverter 특성 연구 (Characteristics of Nanowire CMOS Inverter with Gate Overlap)

  • 유제욱;김윤중;임두혁;김상식
    • 전기학회논문지
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    • 제66권10호
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    • pp.1494-1498
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    • 2017
  • In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage ($V_{dd}$) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high $I_{on}/I_{off}$ ratios are major factors that enable the excellent operation of the logic gate.

ITO Extended Gate Reduced Graphene Oxide Field Effect Transistor For Proton Sensing Application

  • Truong, Thuy Kieu;Nguyen, T.N.T.;Trung, Tran Quang;Son, Il Yung;Kim, Duck Jin;Jung, Jin Heak;Lee, N.E.
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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    • pp.653-653
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    • 2013
  • In this study, ITO extended gate reduced graphene oxide field effect transistor (rGO FET) was demonstrated as a transducer for a proton sensing application. In this structure, the sensing area is isolated from the active area of the device. Therefore, it is easy to deposit or modify the sensing area without affecting on the device performance. In this case, the ITO extended gate was used as a gate electrode as well as a proton sensing material. The proton sensing properties based on the rGO FET transducer were analyzed. The rGO FET device showed a high stability in the air ambient with a TTC encapsulation layer for months. The device showed an ambipolar characteristic with the Dirac point shift with varying the pH solutions. The sensing characteristics have offered the potential for the ion sensing application.

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Design and Analysis of Gate-recessed AlGaN/GaN Fin-type Field-Effect Transistor

  • Jang, Young In;Seo, Jae Hwa;Yoon, Young Jun;Eun, Hye Rim;Kwon, Ra Hee;Lee, Jung-Hee;Kwon, Hyuck-In;Kang, In Man
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권5호
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    • pp.554-562
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    • 2015
  • This paper presents the design and analysis of gate-recessed AlGaN/GaN Fin-type Field-Effect Transistor (FinFET). The three-dimensional (3-D) technology computer-aided design (TCAD) simulations were performed to analyze the direct-current (DC) and radio-frequency (RF) characteristics for AlGaN/GaN FinFETs. The fin width ($W_{fin}$) and the height of GaN layer ($H_{GaN}$) are the design parameters used to improve the electrical performances of gate-recessed AlGaN/GaN FinFET.

Device characterization and Fabrication Issues for Ferroelectric Gate Field Effect Transistor Device

  • Yu, Byoung-Gon;You, In-Kyu;Lee, Won-Jae;Ryu, Sang-Ouk;Kim, Kwi-Dong;Yoon, Sung-Min;Cho, Seong-Mok;Lee, Nam-Yeal;Shin, Woong-Chul
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제2권3호
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    • pp.213-225
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    • 2002
  • Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.

GROWTH AND ELECTRICAL PROPERTIES OF (La,Sr)CoO$_3$/Pb(Zr,Ti)O$_3$/(La,Sr)CoO$_3$ HETEROSTRUCTURES FOR FIELD EFFECT TRANSISTOR

  • Lee, J.;Kim, S.W.
    • 한국표면공학회지
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    • 제29권6호
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    • pp.839-846
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    • 1996
  • Epitaxial (La, Sr)$CoO_3/Pb(Zr,\;Ti)O_3/(La,\;Sr)CoO_3$by pulsed laser deposition for ferroelectric field effect transistor. Epitaxial $LaCoO_3/Pb(Zr,\;Ti)O_3/(La,\;Sr)CoO_3$ heterostructures exhibited 70$\mu C/cm^2$ and 17 $\mu C/cm^2$at a positively and negatively poled states, respectively. On the other hand, epitaxial (La, Sr)$CoO_3/Pb(Zr,\;Ti)O_3/LaCoO_3$heterostructures show the remnant polarization states opposite to the $LaCoO_3/Pb(Zr,\;Ti)O_3/(La,\;Sr)CoO_3$ heterostructures. This indicates that the interface between (La, Sr)$CoO_3$ (LSCO) and $Pb(Zr, Ti)O_3(PZT)$ layers affects the asymmetric polarization remanence through electrochemical nature. The resistivity of $LaCoO_3$ (LCO) layer was found to be dependent on an ambient oxygen, primarily the ambient oxygen pressure during deposition. The resistivity of the LCO layer varied in the range of 0.1-100 $\Omega$cm. It is suggested that, with an appropriate resistivity of the LCO layer, the LCO/PZT/LSCO heterostructure can be used as the ferroelectric field effect transistor.

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