• Title/Summary/Keyword: delay time interval

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Stability of Time-delayed Linear Systems with New Integral Inequality Proportional to Integration Interval (새로운 적분구간 비례 적분 부등식을 이용한 시간지연 선형시스템의 안정성)

  • Kim, Jin-Hoon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.3
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    • pp.457-462
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    • 2016
  • In this paper, we consider the stability of time-delayed linear systems. To derive an LMI form of result, the integral inequality is essential, and Jensen's integral inequality was the best in the last two decades until Seuret's integral inequality is appeared recently. However, these two are proportional to the inverse of integration interval, so another integral inequality is needed to make it in the form of LMI. In this paper, we derive an integral inequality which is proportional to the integration interval which can be easily converted into LMI form without any other inequality. Also, it is shown that Seuret's integral inequality is a special case of our result. Next, based on this new integral inequality, we derive a stability condition in the form of LMI. Finally, we show, by well-known two examples, that our result is less conservative than the recent results.

Design of Low-jilter DLL using Vernier Method (Vernier 방법을 이용한 Low-jitter DLL 구현)

  • 서승영;장일권;곽계달
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.83-86
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    • 2000
  • This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

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An Analog Multi-phase DLL for Harmonic Lock Free (Harmonic Locking을 제거하기 위한 아날로그 Multi- phase DLL 설계)

  • 문장원;곽계달
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.281-284
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    • 2001
  • This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

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Delay-Optimized Adaptive Multichannel Backoff Mechanism for VANET (VANET을 위한 지연 최적화 적응적 멀티 채널 백오프 메카니즘)

  • Lee, Jung-Jae
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.5
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    • pp.837-844
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    • 2019
  • In this paper, we propose the AMBM(: Adaptive Multi-channel Backoff Machisum) -Mac protocol to provide high throughput for non-safety applications in VANET(: Vehicular Ad Hoc Networks) environment. The proposed protocol guarantees the quality of service of non-safety packets by dynamically adjusting CW(: Channel Window) of WSA(: WAVE Service Advertisement) to maximize throughput between non-safety packets of different priority. It also shows that allocating a large amount of time for channel coordination and time slot reservation for SC and dynamically adjusting CW and CCI as nodes increase to reduces transmission delay than IEEE 1609.9, C-MAC(: Coordinated multi-channel MAC, and Q-VCI(: QoS Variable CCH Interval) protocols.

Development of a High Power SONAR System Measuring Velocity by Using Two Gated Sinusoidal Signals (두 개의 정현 신호를 이용한 속도 측정용 고전력 쏘나 시스템 개발)

  • 장순석;안흥구;이제형
    • Journal of KSNVE
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    • v.9 no.5
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    • pp.1036-1041
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    • 1999
  • This paper aims for the development of the high power sonar system for measuring the velocity of a moving object. The high power sonar system transmits two gated 190 kHz sinusoidal signals with 1.6 [ms] time interval to the moving object. Then the sonar system detects and calculates the changed time delay of the reflected ultrasonic signals in order to derive the velocity of the moving object. The transmission part uses a high power amplifier so that 250 W gated sinusoidal signals can be transmitted to the transmitter. 1M RAM is utilized for transmitting and storing of the ultrasonic signals. The time delay is calculted by the cross-correlation technique between the transmitted signals and the received signals. The measured value from the high power sonar system is compared with directly measured values by photo diodes. The result confirms the adjacency to 0.3% error.

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Delay time Analysis of Asynchronous RIT Mode MAC in Wi-SUN (Wi-SUN에서 비동기 RIT모드 MAC의 지연시간 분석)

  • Dongwon Kim;Mi-Hee Yoon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.24 no.2
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    • pp.65-70
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    • 2024
  • In recent years, research on smart factory wireless mobile communication technology that wirelessly remotely controls utilities is being actively conducted. The Wi-SUN (Wireless Smart Utility Network) Alliance proposed a Wi-SUN protocol structure suitable for building a platform such as a smart factory as a new wireless communication standardization standard based on EEE802.15.4g/e. It analyzes the performance of the IEEE802.15.4e Receiver Initiated Transmission(RIT) Mode Media Access Control (MAC) in terms of throughput and latency, and looks at considerations for efficient operation. RIT mode shows that as the check interval becomes longer, delay time and throughput decrease. It was shown that as the traffic load increases, if the RIT check interval is shortened, the delay time can be shortened and throughput can be increased. RIT mode has the advantage of low power consumption and has neutral characteristics between IEEE802.15.4 and CSL mode in terms of delay time and throughput.

Design of Optimized Interval Type-2 Fuzzy Controller and Its Application (최적 Interval Type-2 퍼지 제어기 설계 및 응용)

  • Jang, Han-Jong;Oh, Sung-Kwun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.8
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    • pp.1624-1632
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    • 2009
  • In this study, we introduce the design methodology of an optimized Interval Type-2 fuzzy controller. The fixed MF design of type-1 based FLC leads to the difficulty of rule-based control design for representing the linguistically uncertain expression. In the Type-2 FLC as the expanded type of Type-1 FLC, we can effectively improve the control characteristic by using the footprint of uncertainty(FOU) of membership function. Type-2 FLC has a robust characteristic in the unknown system with unspecific noise when compared with Type-1 FLC. Through computer simulation as well as practical experiment, we compare their performance by applying both the optimized Type-1 and Type-2 fuzzy cascade controllers to ball and beam system. To evaluate each controller performance, we consider controller characteristic parameters such as maximum overshoot, delay time, rise time, settling time and steady-state error.

Mechanism of Multimedia Synchronization using Delay Jitter Time (지연지터시간을 이용한 멀티미디어 동기화 기법)

  • Lee, Keun-Wang;Jun, Ho-Ik
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.11
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    • pp.5512-5517
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    • 2012
  • In this paper we suggest multimedia synchronization model that is based on the Petri-net and services desirable quality of service requirement. Proposed model applies variable buffer which can be allowed, and then it presents high quality of service and real time characteristics. This paper decreases the data loss resulted from variation of delay time and from loss time of media-data by means of applying delay jitter in order to deal with synchronization interval adjustment. Plus, the mechanism adaptively manages the waiting time of smoothing buffer, which leads to minimize the gap from the variation of delay time. The proposed paper is suitable to the system which requires the guarantee of high quality of service and mechanism improves quality of services such as decrease of loss rate, increase of playout rate.

Necessary and Sufficient Stability Condition of Discrete State Delay Systems

  • Suh, Young-Soo;Ro, Young-Shick;Kang, Hee-Jun;Lee, Hong-Hee
    • International Journal of Control, Automation, and Systems
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    • v.2 no.4
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    • pp.501-508
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    • 2004
  • A new method to solve a Lyapunov equation for a discrete delay system is proposed. Using this method, a Lyapunov equation can be solved from a simple linear equation and N-th power of a constant matrix, where N is the state delay. Combining a Lyapunov equation and frequency domain stability, a new stability condition is proposed for a discrete state delay system whose state delay is not exactly known but only known to lie in a certain interval.

Some Properties About the Root Loci for Unity Negative Feedback Control Systems (단일 부궤환 제어시스템의 근궤적에 관한 특성)

  • Kang, Hwan-Il
    • Proceedings of the KIEE Conference
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    • 1996.07b
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    • pp.1005-1008
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    • 1996
  • We consider the interval of a gain within which it is guaranteed that a feedback control system is stable. This paper presents the condition under which either a unity feedback control system is stable for a connected gain interval with a proportional compensator cascaded with an open loop forward transfer function. By the connected interval we mean that all the numbers between any two numbers in the connected interval belongs to the connected interval. The condition may be described by a frequency inequality in terms of the denominator and/or numerator of the closed loop transfer function. We also consider the conditions for the discrete-time control systems and the time delay continuous-time control systems. We show that this condition cannot be extended for the transfer function having complex coefficients via a counterexample.

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