• Journal of applied mathematics & informatics
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• v.28 no.5_6
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• pp.1379-1393
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• 2010

In this paper, a stage-structured predator prey model (stage structure on prey) with two discrete time delays has been discussed. The two discrete time delays occur due to maturation delay and gestation delay. Linear stability analysis for both non-delay as well as with delays reveals that certain thresholds have to be maintained for coexistence. Numerical simulation shows that the system exhibits Hopf bifurcation, resulting in a stable limit cycle.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.10
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• pp.95-102
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• 2003

The buffering is a promising solution to resolve the contention problem in optical network. we study the packet loss probability and the dimensioning of optical buffer using a Fiber Delay Line for variable length packet. In this paper, we study the relation between the granularity and the loss of FDL buffer in Single-Stage FDL buffer and propose the Single-Bundle Multi-Stage FDL buffer. The Multi-Stage FDL buffer is too early yet to apply to the current backbone network, considering the current technology in view of costs. but we assume that the above restriction will be resolved in these days. The appropriate number of delay and pass line for a dimensioning is based on a amount of occupied time by packets. Once more another multi-stage FDL buffer is proposed, Split-Bundle multi-stage FDL buffer. The Split-Bundle ms-FDL buffer is more feasible for a FDL buffer structure, considering not only a size of switching matrix but also a bulk of switching element. its feasibility will be demonstrated from a loss probability.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.50-56
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• 1999

This paper presents a new technique for generating precise clock delays. The technique can obtain finer timing resolution less than the gate delay of the delay chain by locking in multiple clock period. Using this technique, a 250ps of timing resolution could be achieved from a 750ps delay of the single delay stage in a DLL(Delay Locked Loop) structure. The delay chain of the proposed circuit is locked on three times of the clock period and a finer delay resolution than the absolute gate delay is achieved and verified through the simulation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.21-29
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• 2002

This paper describes a high resolution DLL(Delay Locked Loop) using all digital circuits. The proposed architecture is based on the three stage of coarse, fine and ultra fine phase tuning block which has a phase detector, selection block and delay line respectively. The first stage, the ultra fine phase tuning block, is tune to accomplish high resolution using a vernier delay line. The second and third stage, the coarse and fine tuning block, are tuning the phase margin of Unit Delay using the delay line and are similar to each other. It was simulated in 0.35um CMOS technology under 3.3V supply using HSPICE simulator. The simulation result shows the phase resolution can be down to lops with the operating range of 250MHz to 800MHz.

• Transactions of the Korean Society of Automotive Engineers
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• v.18 no.2
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• pp.97-103
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• 2010

The four combustion stages in a diesel engine have close correlation among them. Especially, the ignition delay period has significant effect on the following combustion stage. And the period is also one of inevitable combustion processes in the diesel engine. For example, the diesel knocking is a well-known phenomenon due to the long ignition delay period. The interval of the ignition delay period is affected by the mixture formation process in the cylinder. However, in the case of the D.I. diesel engine, the available duration to make the mixture formation of air-fuel is very short. In addition, the means of the mixture formation mainly depends on the injection characteristics and properties of the fuel. It is difficult to make complete mixture. Therefore, an early stage of combustion is violent, which leads to the weakness of noise and vibration. In this study, using the visible engine, we measured the ignition delay period by photo sensor which detect occurrence of flame and presented the factors of the injection characteristics such as kinds of injection system, the injection pressure and the injection timing. The relation between the ignition delay period and cylinder pressure diagram which was concurrently obtained was also estimated.

• Journal of applied mathematics & informatics
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• v.28 no.1_2
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• pp.193-207
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• 2010

In this paper, a predator-prey model with stage structure and distributed delay is investigated. Mathematical analyses of the model equation with regard to boundedness of solutions, nature of equilibria, permanence, extinction and stability are performed. By the comparison theorem, a set of easily verifiable sufficient conditions are obtained for the global asymptotic stability of nonnegative equilibria of the model. Taking the product of the per-capita rate of predation and the rate of conversing prey into predator as the bifurcating parameter, we prove that there exists a threshold value beyond which the positive equilibrium bifurcates towards a periodic solution.

• Kyungpook Mathematical Journal
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• v.49 no.4
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• pp.605-618
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• 2009

A stage-structured predator-prey system with time delay and Beddington-DeAngelis functional response is considered. By analyzing the corresponding characteristic equation, the local stability of a positive equilibrium is investigated. The existence of Hopf bifurcations is established. Formulae are derived to determine the direction of bifurcations and the stability of bifurcating periodic solutions by using the normal form theory and center manifold theorem. Numerical simulations are carried out to illustrate the theoretical results.

• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.85-89
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• 1998

A switching power stage is a very nonlinear system because it has two or more operation modes in one switching cycle. To model a switching power stage, the state space averaging method has been developed. Though it allows a unified treatment of a large variety of switching power stages, the model it yields is always very nonlinear. So, it is required to linearize the averaged model. But it is well known that a controller for a nonlinear plant designed by the linearization frequently fails in showing satisfactory control performance. Hence it is very natural to try to design a nonlinear controller for a switching power stage. In design of a switching power system, nonlinear control approaches such as adaptive control and fuzzy control have been widely studied so far. In this research, a recently developed control method, time delay control is briefly studied and a design example for a ZVS PWM half bridge converter is given. The performance of the time delay controller is compared to its conventional counterpart, PI controller by computer simulations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.