• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.5
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• pp.1104-1109
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• 2015

Due to the rapid growth in digital contents, it is important for us to design a high speed and secure encryption algorithm which is able to comply with the existing and future needs. This paper proposes an alternative approach for self-decimated LM-128 summation sequence generator, which will generate a higher throughput if compared to the conventional generator. We design and implement a threshold clock-controlled LM-128 and prove that it has a lower clock cycle and hence giving a higher key stream generation speed. The proposed threshold clock-control LM-128 generator consists of 256 bits inner state with 128 bits secret key and initialization vector. The cipher achieves a security level of 128 bits to be adapted to the digital contents security with high definition and high quality.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.188-193
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• 2003

This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.

• ETRI Journal
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• v.33 no.5
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• pp.752-758
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• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

• Journal of Photoscience
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• v.9 no.2
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• pp.25-28
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• 2002

The chicken pineal gland has been used for studies on the circadian clock, because it retains an intracellular phototransduction pathway regulating the phase of the intrinsic clock oscillator. Previously, we identified chicken clock genes expressed in the gland (cPer2, cPer3, cBmal1, cBmal2, cCry1, cCry2, and cClock), and showed that a cBMALl/2-cCLOCK heteromer acts as a regulator transactivating cPer2 gene through the CACGTG E-box element found in its promoter. Notably, mRNA expression of cPer2 gene is up-regulated by light as well as is driven by the circadian clock, implying that light-dependent clock resetting may involve the up-regulation of cPer2 gene. To explore the mechanism of light-dependent gene expression unidentified in animals, we first focused on pinopsin gene whose mRNA level is also up-regulated by light. A pinopsin promoter was isolated and analyzed by transcriptional assays using cultured chicken pineal cells, resulting in identification of an 18-bp light-responsive element that includes a CACGTG E-box sequence. We also investigated a role of mitogen-activated protein kinase (MAPK) in the clock resetting, especially in the E-box-dependent transcriptional regulation, because MAPK is phospholylated (activated) in a circadian manner and is rapidly dephosphorylated by light in the gland. Both pulldown analysis and kinase assay revealed that MAPK directly associates with BMAL1 to phosphorylate it at several Ser/Thr residues. Transcriptional analyses implied that the MAPK-mediated phosphorylation may negatively regulate the BMAL-CLOCK-dependent transactivation through the E-box. These results suggest that the CACGTG E-box serves not only as a clock-controlled element but also as a light-responsive element.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• Journal of Life Science
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• v.23 no.1
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• pp.8-14
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• 2013

Genes expressed during conidial germination of the pepper anthracnose fungus Colletotrichum acutatum were identified by sequencing the 5' end of unidirectional cDNA clones prepared from the conidial germination stage. A total of 983 expressed sequence tags (ESTs) corresponding to 464 genes, 197 contigs and 267 singletons, were generated. The deduced protein sequences from half of the 464 genes showed significant matches (e value less than 10-5) to proteins in public databases. The genes with known homologs were assigned to known functional categories. The most abundantly expressed genes belonged to those encoding the elongation factor, histone protein, ATP synthease, 14-3-3 protein, and clock controlled protein. A number of genes encoding proteins such as the GTP-binding protein, MAP kinase, transaldolase, and ABC transporter were detected. These genes are thought to be involved in the development of fungal cells. A putative pathogenicity function could be assigned for the genes of ATP citrate lyase, CAP20 and manganese-superoxide dismutase.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1210-1217
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• 2004

LILI-II stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE. Since the algorithm is a clock-controlled, the speed of the keystream data is degraded structurally in a clock-synchronized hardware logic design. Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback or shifting within the LFSR. furthermore, the timing of the proposed design is simulated using a Max+plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C, 0.13${\mu}{\textrm}{m}$ CMOS ＆ 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13${\mu}{\textrm}{m}$ semiconductor for the maximum path delay below 1.8㎱. Finally, we propose the m-parallel implementation of LILI-II, throughput with 4, 8 or 16 Gbps (m=8, 16 or 32).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2283-2291
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• 2010

The shrinking generator which is one of clock-controlled generator is a very simple generator with good cryptographic properties. A nonlinear sequence generator based on two 90/150 maximum length cellular automata can generate pseudorandom sequences at each cell of cellular automata whose characteristic polynomials are same. The nonlinear sequence generated by cellular automata has a larger period and a higher linear complexity than shrunken sequence generated by LFSRs. In this paper we analyze shrunken-interleaved sequence based on 90/150 maximum length cellular automata. We show that the sequence generated by nonlinear sequence generator based on cellular automata belongs to the class of interleaved sequence. And we give an effective algorithm for reconstructing unknown bits of output sequence based on intercepted keystream bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.