• Journal of IKEEE
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• v.24 no.1
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• pp.284-292
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• 2020

SiC-based devices perform well in high-voltage environments of more than 1200V compared to silicon devices, and are particularly stable at very high temperatures. Therefore, 1700V UMOSFET has been actively researched and developed for the use of electric power systems such as electric vehicles and aircrafts. In this paper, we analysed thermal variations of critical variables (breakdown voltage (BV), on-resistance (R_on), threshold voltage (v_th), and transconductance (g_m)) for the three type 1700V UMOSFETs-Conventional UMOSFET (C-UMOSFET), Source Trench UMOSFET (ST-UMOSFET), and Local Floating Superjunction UMOSFET (LFS-UMOSFET). All three devices showed BV increase, R_on increase, v_th decrease, and g_m decrease with increasing temperature. However, there are differences in BV, R_on, v_th, g_m according to the structural differences of the three devices, and the degree and cause of the analysis were compared. All results were simulated using sentaurus TCAD.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.6
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• pp.104-108
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• 2009

The insulation aging characteristics and structural analysis test were performed to analyze the correlations among the insulation deterioration, diagnostic results and the breakdown strength for the underground power cables. From the results of the degree of crosslinking test, hot-oil test etc., it could be confirmed that there were no manufacturing defects in the power cables under test. From the results of the water tree test and chemical structural analysis, it could be confirmed that the aging status of cable under test were very poor, especially for B-Phase and the degree of aging was increased in the orders of A, C and B-phase. From the above results, it could be concluded that the insulation aging characteristic analysis results were well consistent with the diagnostic and breakdown test results, and also confirmed that the diagnostic system under consideration was successful to discriminate the bad cables which is likely to cause cable system failure.

• Korean Journal of Materials Research
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• v.29 no.3
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• pp.175-182
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• 2019

This study examines paraelectric $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN), which has no hysteresis and high dielectric strength, for energy density capacitor applications. To increase the breakdown dielectric strength of the BZN film further, poly(vinylidene fluoride) BZN-PVDF composite film is fabricated by aerosol deposition. The volume ratio of each composition is calculated using dielectric constant of each composition, and we find that it was 12:88 vol% (BZN:PVDF). To modulate the structure and dielectric properties of the ferroelectric polymer PVDF, the composite film is heat-treated at $200^{\circ}C$ for 5 and 30 minutes following quenching. The amount of ${\alpha}-phase$ in the PVDF increases with an increasing annealing time, which in turn decreases the dielectric constant and dielectric loss. The breakdown dielectric strength of the BZN film increases by mixing PVDF. However, the breakdown field decreases with an increasing annealing time. The BZN-PVDF composite film has the energy density of $4.9J/cm^3$, which is larger than that of the pure BZN film of $3.6J/cm^3$.

• Journal of IKEEE
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• v.26 no.3
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• pp.333-340
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• 2022

Process and device simulations were performed to determine the optimal ion implantation conditions to prevent double snapback of high voltage operating DDDNMOS (double diffused drain N-type MOSFET) device for ESD protection. By examining the effects of HP-Well, N^- drift and N⁺ drain ion implantation on the double snapback and avalanche breakdown voltages, it was possible to prevent double snapback and improve the electrostatic protection performance. If the ion implantation concentration of the N^- drift region rather than the HP-Well region is optimally designed, it prevents the transition from the primary on-state to the secondary on-state, so that relatively good ESD protection performance can be obtained. Since the concentration of the N^- drift region affects the leakage current and the avalanche breakdown voltage, in the case of a process technology with an operating voltage greater than 30V, a new structure such as DPS or colligation of optimal process conditions can be applied. In this case, improved ESD protection performance can be realized.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1129-1132
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• 1995

In the preparation of the layered $BaTiO_3$ thin films with high performance, the new stacking method using the continuous cooling of the substrate was introduced. Amorphous/polycrystalline $BaTiO_3$ layered structure was confirmed by SEM and index of refraction. The layered $BaTiO_3$ thin films formed by the new stacking method showed such a high dielectric constant that the layered structure could not be explained by a stacking structure of the two defined layers but could only be explained by multi-layered structure, i.e. amorphous/micro crystalline/polycrystalline structure. The layered $BaTiO_3$ thin film with a thickness of 240 nm showed higher capacitance per unit area and breakdown strength than the double layered $BaTiO_3$ thin film prepared by the conventional stacking method. And well defined ferroelectric hysteresis leer was observed in the layered $BaTiO_3$ thin film with a thickness of 200 nm.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.1-5
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW_PGM(primary gate middle) and optimal CPS(counter pocket source) implant demonstrate the stable ESD protection performance with high latch-up immunity.

• ETRI Journal
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• v.38 no.2
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• pp.272-279
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• 2016

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.63-68
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• 2014

Electrostatic Discharge(ESD) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW demonstrate the stable ESD protection performance with high latch-up immunity.

• Journal of the Society of Naval Architects of Korea
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• v.56 no.1
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• pp.1-10
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• 2019

Naval ship design and related other activities can be characterized by the complexity of the interactions among products, activities, and disciplines. Such complexities often result in inferior designs, cost overrun, and late-delivery. Hence there exist tremendous interests in both improving the design process itself and optimizing the interactions among design activities. This paper looks at the complexity of designing naval ships thereby leading to the innovation of current ship design practices using design structure matrix. It can be used to induce the optimal ordering of design activities as well as identify sources of complexities. The method presented here identifies coupled design activities useful for reducing the complexity of naval ship design as well as optimally reordering design activities. This paper recommends the use of design structure matrix method suitable for numerically optimizing the concept design process of naval ship, and reducing cost and time required in designing naval ships by modeling and analyzing the design activities and engineering tasks, defined in systems engineering planning documents.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1897-1899
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• 2004

In this paper, in order to analyze the characteristics of degradation by salt water with insulation cover and OC wire(outdoor cross-linked polyethylene insulated wire) used in power receiving system, an experimental apparatus has been designed and fabricated. An insulation cover and OC wire were installed in an experimental apparatus, and degraded in each case of 2%, 5%, 10% salinity during 12 weeks. An optical microscope was used to observe a changing process of sample surface, and an electrical safety was analyzed by measuring dielectric breakdown voltages of samples. As salinity increased, so ununiformity of sample surface increased. The breakdown wasn't produced to 50kV about samples regardless of salinity, testing period.