• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.33 no.3
• /
• pp.427-435
• /
• 2023

Cardinality estimation is used in wide range of applications and a fundamental problem processing a large range of data. While the internet moves into the era of big data, the function addressing cardinality estimation use only on-chip cache memory. To use memory efficiently, there have been various methods proposed. However, because of the noises between estimator, which is data structure per flow, loss of accuracy occurs in these algorithms. In this paper, we focus on minimizing noises. We propose multiple data structure that each estimator has the number of estimated value as many as the number of structures and choose the minimum value, which is one with minimum noises, We discover that the proposed algorithm achieves better performance than the best existing work using the same tight memory, such as 1 bit per flow, through experiment.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.12C
• /
• pp.1209-1216
• /
• 2003

The transcoding is needed to modify the bit rate of the video bitstream in accordance with the bandwidth of a variety of channels in order to provide users with a realtime multimedia service and more stable and credible VOD(Video On Demand) service on various wire/wireless network. This paper suggests how to guarantee the video quality in the transcoding process, taking the activity and direction of the macroblock into consideration, thereby reducing the calculation. The threshold of the macroblock's activity and direction is applicable to the different videos, with the DCT coefficients from the intermediate data in the decoding process. Moreover, the suggested video transcoding algorism enables us to maintain the proper video quality and reduce the calculation through the video bit rate change experiment in H.263 environment.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.1
• /
• pp.131-143
• /
• 1996

In this paper, we propose the improved structure of fully interconnected ATM Switch to develop the small sized switch element and represent practical implementation of switch network. As the part II of the full study about structure and implementation of fully interconnected ATM Switch, this paper especially describes the implementation of an ATM switching element with 8 input port and 8 output port at 155 Mbits/sec each. The single board switching element is used as a basic switching block in a small sized ATm switch for ATM LAN Hub and customer access node. This switch has dedicated bus in 12 bit width(8 bit data + 4 bit control signal) at each input and output port, bit addressing and cell filtering scheme. In this paper, we propose a practical switch architecture with fully interconnected buses to implement a small-sized switch and to provide multicast function withoutany difficulty. The design of switching element has become feasible using advanced CMOS technology and Embedded Gate Array technology. And, we also represent Application Specific Integrated Circuit(ASIC) of Switch Output Multiplexing Unit(SOMU) and 12 layered Printed Circuit Board for interconnection network of switch.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.5
• /
• pp.66-73
• /
• 2015

IFFT is one of the key components in OFDM-based communication systems. In this paper, we propose a new memory efficient IFFT design method for OFDM-based communication systems, based on a mapping of three IFFT input signals which consist of modulated data, pilot and null signals. The proposed method focuses on reducing the memory size in the bit-reversal block which requires the largest number of memory cells in IFFT architectures. To reduce the memory size, we propose a selection mapping method based on decimation-in-time (DIT) algorithm. It is shown that the proposed method achieves a memory reduction of about 50% compared to conventional methods.

• ETRI Journal
• /
• v.30 no.3
• /
• pp.377-382
• /
• 2008

A novel power amplifier for a polar transmitter is proposed to achieve better spectral performance for a wideband envelope signal. In the proposed scheme, 2-bit sigma-delta (${\Sigma}{\Delta}$) modulation of the envelope signal is introduced, and the power amplifier configuration is modified in a binary form to accommodate the 2-bit digitized envelope signals. The 2-bit ${\Sigma}{\Delta}$ modulator lowers the noise of the envelope signal by fine quantization and thus enhances the spectral property of the RF signal. The Ptolemy simulation results of the proposed structure show that the spectral noise is reduced by 10 dB in a full transmit band of the EDGE system. The dynamic range is also enhanced. Since the performance is improved without increasing the over-sampling ratio, this technique is best suited for wireless communication with high data rates.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.11 no.3
• /
• pp.153-163
• /
• 1986

GaAs, one of the III-V compounding semicondnctors, has been widely employed as base materials for the fabrication of the ultra-high-speed devices in the filelds of DBS, optical communications, MMIC'S and digital IC'S. There have been some reports on 4Kx4bit SRAM by D/E MESFET'S, 4K bit SRAM by HEMT'S, and receiver front ends for X-band by MMIC technologies, respectively. This paper reviews GaAs materials, wafer fabrication processes, device applications, and design aspects, and, finally, descusses the future of the ultra-high-spped-devices.

• Transactions on Electrical and Electronic Materials
• /
• v.11 no.5
• /
• pp.238-241
• /
• 2010

The purpose of this study is to solve the problems of radio frequency bandwidth frequency depletion, confusion possibilities, and security that are in current wireless communications systems, and to confirm the possibility of applying those solutions for the next generation network. To solve the problems of the current wireless communications system, a visible light communications system for power line communication (PLC) via 8-bit microcontroller is created and the capacity is analyzed. The exclusive PLC chip APLC-485MA, an 8-bit ATmega16 microcontroller, high brightness 5pi light emitting diodes (LEDs), and the LLS08-A1 visible light-receiving sensor were used for the transmitter and receiver. The performance was analyzed using a designed program and an oscilloscope. The voltage change was measured as a function of distance from 10-50 cm. Blue LEDs showed the best performance among the measured LED types, with 0.47 V of voltage loss, but for a distance over 50 cm, precise data was not easy to obtain due to the weak light. To overcome these types of problems, specific values such as the changing conditions and efficiency value relevant to the light emitting parts and the visible light-receiving sensor should be calculated, and continuous study and improvements should also be realized for better communication conditions.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.305-308
• /
• 2002

An 1.8V 6bit IGSPS ADC for high speed data acquisition is discussed in this paper. This ADC is based on a flash ADC architecture because the flash ADC is the only practical architecture at conversion rates of IGSPS and beyond. A straightforward 6bit full flash A/D converter consists of two resistive ladders with 63 laps, 63 comparators and digital blocks. One important source of errors in flash A/D converter is caused by the capacitive feedthrough of the high frequency input signal to the resistive reference-lauder. Consequently. the voltage at each tap of the ladder network can change its nominal DC value. This means large transistors have a large parasitic capacitance. Therefore, a dual resistive ladder with capacitor is employed to fix the DC value. Each resistive ladder generates 32 clean reference voltages which alternates with each other. And a two-stage amplifier is also used to reduce the effect of the capacitive feedthrough by minimizing the size of MOS connected to reference voltage. The proposed ADC is based on 0.18${\mu}{\textrm}{m}$ 1-poly 6-metal n-well CMOS technology, and it consumes 307㎽ at 1.8V power supply.

• Proceedings of the IEEK Conference
• /
• summer
• /
• pp.199-203
• /
• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.6
• /
• pp.15-20
• /
• 2015

Bit patterned media (BPM) is a high capacity storage system and has attracted a great deal of attention as next generation data storage. When BPM is made with high density, the space between the islands narrows, because BPM records one bit in an island. For this reason, BPM has inter-symbol interference in all directions, unlike in current storage systems where it is in only one direction. In this paper, we propose an equation for compensating two-dimensional ISI. We conduct experiments on track misregistration. When using the proposed inter-symbol interference preprocessing, the BER performance is improved, regardless of the amount of track misregistration.