• Nuclear Engineering and Technology
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• v.43 no.4
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• pp.391-398
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• 2011

The U metal chips generated in developing nuclear fuel and a gamma radioisotope shield have been stored under immersion of water in KAERI. When the water of the storing vessels vaporizes or drains due to unexpected leaking, the U metal chips are able to open to air. A new oxidation treatment process was raised for a long time safe storage with concepts of drying under vacuum, evaporating the containing water and organic material with elevating temperature, and oxidizing the uranium metal chips at an appropriate high temperature under conditions of controlling the feeding rate of oxygen gas. In order to optimize the oxidation process the uranium metal chips were completely dried at higher temperature than $300^{\circ}C$ and tested for oxidation at various temperatures, which are $300^{\circ}C$, $400^{\circ}C$, and $500^{\circ}C$. When the oxidation temperature was $400^{\circ}C$, the oxidized sample for 7 hours showed a temperature rise of $60^{\circ}C$ in the self-ignition test. But the oxidized sample for 14 hours revealed a slight temperature rise of $7^{\circ}C$ representing a stable behavior in the self-ignition test. When the temperature was $500^{\circ}C$, the shorter oxidation for 7 hours appeared to be enough because the self-ignition test represented no temperature rise. By using several chemical analyses such as carbon content determination, X-ray deflection (XRD), Infrared spectra (IR) and Thermal gravimetric analysis (TGA) on the oxidation treated samples, the results of self-ignition test of new oxidation treatment process for U metal chip were interpreted and supported.

• Resources Recycling
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• v.4 no.1
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• pp.25-30
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• 1995

In the preparatIon of reclaimed aluminium lllgot from alumimum scrap, the aluminium recovery was studied a as a function of the preliminary treatment of samples, addition of flux and melting atmosphere. AI dross is produced by an oxidation reaction at the surface of liquid metal. The recovery of AI metal increases u up to maximum 95% by adding salt up to 7%, The recovery of AI metal in the compacted chip bale without oil removal mcrease about 14% compared io non-compacted chip. In the case of the AI seed melting process, the recovery of Al metal of the crushed and compacted chip hale is 97%, In meltmg of alumimum scrap under the atmosphere of carbon and nitrogen gas, the recovery of AI metal increase, but it is decreased when the mixture of salt and carbon powder is added excessively.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.294-301
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• 2017

This paper presents a low power ${\Sigma}{\Delta}$ modulator for an implantable chip to acquire a bio-signal such as EEG, DBS, and EMG. In order to reduce a power consumption of the proposed fourth order modulator, two op-amps utilized for the first two integrators are reconfigured to drive the second two integrators. The KT/C noise reduction circuit in the first two integrators is employed to enhance SNR of the modulator. The proposed circuit was fabricated in a 0.18 um CMOS n-well 1 poly 6 metal process with the active chip core area of $900um{\times}800um$ and the power consumption of 830 uW. Measurement results were demonstrated to be SNDR of 76 dB, DR of 77 dB, ENOB of 12.3 bit at the input frequency of 250 Hz and the clock frequency of 256 kHz. FOM1 and FOM2 were measured to be 41 pJ/step and 142.4 dB, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.4 s.310
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• pp.53-59
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• 2006

This paper describes the new design technique of full wave rectifier (FWR) for precise measurement instrument and the chip implementation of this FWR circuit with measurement results. Conventional circuits have some problems of complex design and limited output range( $VDD/2{\sim}VLIIV1IT+$). Proposed FWR circuit was simply designed with two 2x1 MUXs, one high speed comparator, and one differential difference amplifier(DDA). One rail-to-rail differential difference amplifier(DDA) performs the DC level shifting to VSS and 2X amplification simultaneously, and enables the full range ($Vss{\sim}VDD$) operation. The proposed FWR circuits shows more than 50% reduction of chip area and power consumption compared to conventional one. Proposed circuit was implemented with 0.35um 1-poly 2-metal CMOS process. Core size is $150um{\times}450um$ and power dissipation is 840uW with 3.3V single supply.

• Journal of IKEEE
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• v.16 no.4
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• pp.343-348
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• 2012

A 11b 100KS/s Algorithmic ADC for Digital PFC controller is proposed. The proposed Algorithmic ADC structure for 11bit resolution is based on a cyclic architecture to reduce chip area and power consumption. The prototype Algorithmic ADC implemented with a 0.18um 1Poly-3Metal CMOS process shows a SNDR 66.7dB and ENOB 10.78bits. And the current consumption is about 780uA at 100KS/s and 5V. The occupied active die area is $0.27mm^2$.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.111.2-111.2
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• 2011

야금학적 방법을 통한 태양전지용 실리콘 제조를 위하여 아크로(Arc furnace)에서 제조된 용융 상태의 금속급 실리콘을 슬래그와 직접 반응시켜 불순물을 제거하는 공정에 관한 연구를 수행하였다. 이를 위해 아크로와 고주파 유도용해로(High-frequency induction furnace)를 이용하여 금속급 실리콘을 제조와 정련 특성 실험을 수행하였다. 본 연구에서 금속급 실리콘을 제조하기 위한 장비로 150kW급-DC 아크로와 300kW급-AC 아크로를 사용하였다. 원재료로 규석, 코크스(Cokes), 숯, 그리고 우드칩(Wood chip)을 실험 비율에 맞춰 아크로 내부에 장입하고, 이를 용융환원 방법을 통해 반응을 시켰다. 이때 생산된 금속급 실리콘의 순도는 약 99.2~99.8% 이었으며, 원재료의 순도, 장입 비율 및 아크로 운전 특성에 따라 편차가 있다. 아크로에서 생산된 금속급 실리콘의 경우 인(phosphorus), 붕소(boron)를 다량 함유하고 있고, 이를 제거하기 위하여 50kW급 고주파 유도용해로 장비를 사용하여 슬래그 정련 실험을 수행하였다. 슬래그 정련시 사용한 성분은 SiO2, CaO 그리고 CaF2 이며, 금속급 실리콘과 슬래그의 질량비 및 반응 시간에 따른 실리콘 불순물 특성을 평가하였다. 실험결과 인과 붕소는 각각 1 ppm 이하, 5 ppm 이하 였으며, 칼슘을 제외한 대부분의 금속 불순물의 경우 0.1~0.2% 임을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.861-862
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• 2015

In this paper we present a low area 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter). The proposed circuit is fabricated using Magnachip/SK Hynix 1-Poly 6-Metal $0.18-{\mu}m$ CMOS process, and it is powered by a 1.8-V supply. Total chip area is reduced by replacing the MIM capacitors with MOS capacitors instead of the capacitors consisting of overall part in chip area. The proposed circuit showed improved power dissipation of 1.9mW, and chip area of $0.45mm^2$ as compared to conventional research results at the power supply of 1.8V. The designed circuit also showed high SNDR (Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective number of bits of 11.4bits.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.485-486
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• 2006

This paper proposes a novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In this temperature sensor, ring oscillators composed of cascaded inverter stages are used to obtain the temperature of the chip. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on analog bandgap reference circuits. The proposed CMOS temperature sensor was fabricated with 80 nm 3-metal DRAM process. It occupies a silicon area of only about less than $0.02\;mm^2$ at $10^{\circ}C$ resolution with under 5uW power consumption at 1 sample/s processing rate. This area is about 33% of conventional temperature sensor in mobile DRAM.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.13 no.1
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• pp.46-52
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• 2014

In this paper, we present a design of meander type microstrip patch antenna which has the best quality in RFID approved international standard of 910MHz broadband, usable in metal environment. In order to be fit into the commercial tag chip on the antenna, a square shaped feeder is installed on the main body as well as in the main body. In addition, a multi meander type patching element was designed in order to reduce the main body effectively. Three antennae, Cases 1, 2 and 3, were designed and compared in the areas of broad band width, effectiveness or recognition distance according to their sizes and number of folds. The measurement result of Case 3 was determined to be the best. It was confirmed that mostly the efficiency and characteristic gain change due to antenna size and number of folds in meander type influenced the antenna recognition distance.