Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Design of a Algorithmic ADC for Digital PFC Controller

Digital PFC Controller를 위한 Algorithmic ADC 설계

  • Jang, Ki-Chang (School of Electrical and Computer Engineering. University of Seoul) ;
  • Kim, Jin-Yong (School of Electrical and Computer Engineering. University of Seoul) ;
  • Hwang, Sang-Hoon (Samsung Electro-Mechanics Co., ltd.) ;
  • Choi, Joong-Ho (School of Electrical and Computer Engineering. University of Seoul)
  • Received : 2012.07.02
  • Accepted : 2012.11.27
  • Published : 2012.12.31
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Abstract

A 11b 100KS/s Algorithmic ADC for Digital PFC controller is proposed. The proposed Algorithmic ADC structure for 11bit resolution is based on a cyclic architecture to reduce chip area and power consumption. The prototype Algorithmic ADC implemented with a 0.18um 1Poly-3Metal CMOS process shows a SNDR 66.7dB and ENOB 10.78bits. And the current consumption is about 780uA at 100KS/s and 5V. The occupied active die area is $0.27mm^2$.

본 논문에서는 Digital PFC Controller에 적합한 11비트 100KS/s의 Algorithmic ADC를 설계하였다. 설계한 Algorithmic ADC는 PFC controller에 적합한 11비트 해상도를 만족하면서 반복적인 순환구조의 동작으로 인해 전체 크기를 줄일 뿐 아니라 소비 전류를 최소화 할 수 있다. 본 논문의 Algorithmic ADC는 0.18um 1Poly-3Metal의 CMOS 공정으로 제작 되었으며 100KS/s의 동작 속도에 SNDR 66.7dB, ENOB 10.78비트의 성능을 가진다. 또한 소비전류는 5V 전원 전압에서 780uA이며 설계된 ADC의 칩 면적은 $0.27mm^2$이다.

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References

  1. Seong-Mok Yu, Joon-Ho Park, Jong-Tae Park, Chong-Gun Yu, "Design of a Tripple-Mode DC-DC Buck Converter ," Journal of IKEEE, v.15, no.2 pp. 134-142, 2011.
  2. Seong-Mok Yu, Joon-Ho Park, Jong-Tae Park, Chong-Gun Yu, "Load Adaptive Control for Mixed-signal PFC Control IC," Power Electronics and Drive Systems, pp. 1222-1227, 2009.
  3. B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995.
  4. P. E. Allen, and D. R. Holberg, CMOS Analog Circuit Design, 2nd ed, Oxford, 2002.
  5. O. E. Erdogan, P. J. Hurst, and S. H. Lewis, "A 12-b digital-background-calibrated algorithmic ADC with -90 dB THD," IEEE International Solid-State Circuits Conference, pp. 316-317, Feb. 1999.
  6. P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, "A ratio-independent algorithmic analog-to-digital conversion technique," IEEE Journal of Solid-State Circuits, vol. 19, No. 6, pp. 828-836, Dec. 1984. https://doi.org/10.1109/JSSC.1984.1052233
  7. C. C. Shih, P. W. Li, and P. Gray, "Ratio independent cyclic A/D and D/A conversion using a recirculating reference approach," IEEE Transactions on Circuits and Systems, vol. 30, No. 10, pp. 772-774, Oct. 1983. https://doi.org/10.1109/TCS.1983.1085291
  8. B. Ginetti, P. G. A. Jespers, and A. Vandemeulebroecke, "A CMOS 13-b cyclic RSD A/D converter," IEEE Journal of Solid-State Circuits, vol. 27, No. 7, pp. 957-964, July 1992. https://doi.org/10.1109/JSSC.1992.854935
  9. Nagari, A. Nicollini, G, "A 2.7V 350$\mu$W 11-b algorithmic analogue-to-digital converter with single-ended multiplexed inputs," Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, vol. 1, pp. 76-81, Feb 2004.