• Journal of IKEEE
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• v.16 no.4
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• pp.343-348
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• 2012

A 11b 100KS/s Algorithmic ADC for Digital PFC controller is proposed. The proposed Algorithmic ADC structure for 11bit resolution is based on a cyclic architecture to reduce chip area and power consumption. The prototype Algorithmic ADC implemented with a 0.18um 1Poly-3Metal CMOS process shows a SNDR 66.7dB and ENOB 10.78bits. And the current consumption is about 780uA at 100KS/s and 5V. The occupied active die area is $0.27mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.280-285
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• 2004

In this paper, a 9-bit analog-to-digital converter (ADC) is designed for optical disk drive (ODD) servo applications. In the ADC, the circuit technique to increase the operating range of the sample-and-hold amplifier is proposed, which can process the wide-varying input common-mode range. The algorithmic ADC structure is chosen so that the area can be significantly reduced, which is suitable for SoC integration. The ADC is fabricated in a 0.18-$\mu\textrm{m} $ CMOS 1P5M technology. Measurement results of the ADC show that SNDR is 51.5dB for the sampling rate of 6.5MS/s. The power dissipation is 36.3mW for a single supply voltage of 3.3V.