• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.914-920
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• 2000

When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.25.2-25.2
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• 2011

Recently, thin film capacitors used for vehicle inverters are small size, high capacitance, fast response, and large capacitance. But its applications were made up of liquid as electrolyte, so its capacitors are limited to low operating temperature range and the polarity. This research proposes using Ni-P alloys by electroless plating as the electrode instead of liquid electrode. Our substrate has a high aspect ratio and complicated shape because of anodic aluminum oxide (AAO). We used AAO because film thickness and effective surface area are depended on for high capacitance. As the metal electrode instead of electrolyte is injected into AAO, the film capacitor has advantages high voltage, wide operating temperature, and excellent frequency property. However, thin film capacitor made by electroless-plated Ni on AAO for full-filling into etched tunnel was limited from optimizing the deposition process so as to prevent open-through pore structures at the electroless plating owing to complicated morphological structure. In this paper, the electroless plating parameters are controlled by temperature in electroless Ni plating for reducing reaction rate. The Electrical properties with I-V and capacitance density were measured. By using nickel electrode, the capacitance density for the etched and Ni electroless plated films was 100 nFcm-2 while that for a film without any etch tunnel was 12.5 nFcm-2. Breakdown voltage and leakage current are improved, as the properties of metal deposition by electroless plating. The synthesized final nanostructures were characterized by scanning electron microscopy (SEM).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.4
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• pp.332-340
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• 2023

Crystalline silicon solar cells have attracted great attention for their various advantages, such as the availability of raw materials, high-efficiency potential, and well-established processing sequence. Tunnel oxide passivated contact (TOPCon) solar cells are widely regarded as one of the most prospective candidates for the next generation of high-performance solar cells because an efficiency of 26% has been achieved in small-area solar cells. Compared to n-type TOPCon solar cells, the photo conversion efficiency (PCE) of p-type TOPCon is slightly higher. The highest PCEs of p-type TOPCon and n-type TOPCon solar cells are 26.0% and 25.8%, respectively. Despite the highest efficiency in small-area cells, limited progress has been achieved in p-type TOPCon solar cells for large are due to their lower carrier lifetime and inferior surface passivation with the boron-doped c-Si wafer. Nevertheless, it is of great importance to promoting the p-type TOPCon technology due to its lower price and well-established manufacturing procedures with slight modifications in the PERC solar cells production lines. The progress in different approaches to increase the efficiencies of p-type TOPCon solar cells has been reported in this review article and is expected to set valuable strategies to promote the passivation technology of p-type TOPCon, which could further increase the efficiency of TOPCon solar cells.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.310-310
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• 2016

최근 NAND flash memory는 높은 집적성과 데이터의 비휘발성, 낮은 소비전력, 간단한 입, 출력 등의 장점들로 인해 핸드폰, MP3, USB 등의 휴대용 저장 장치 및 노트북 시장에서 많이 이용되어 왔다. 특히, 최근에는 smart watch, wearable device등과 같은 차세대 디스플레이 소자에 대한 관심이 증가함에 따라 유연하고 투명한 메모리 소자에 대한 연구가 다양하게 진행되고 있다. 대표적인 플래시 메모리 소자의 구조로 charge trapping type flash memory (CTF)가 있다. CTF 메모리 소자는 trap layer의 trap site를 이용하여 메모리 동작을 하는 소자이다. 하지만 작은 window의 크기, trap site의 열화로 인해 메모리 특성이 나빠지는 문제점 등이 있다. 따라서 최근, trap layer에 다양한 물질을 적용하여 CTF 소자의 문제점을 해결하고자 하는 연구들이 진행되고 있다. 특히, 산화물 반도체인 zinc oxide (ZnO)를 trap layer로 하는 CTF 메모리 소자가 최근 몇몇 보고 되었다. 산화물 반도체인 ZnO는 n-type 반도체이며, shallow와 deep trap site를 동시에 가지고 있는 독특한 물질이다. 이 특성으로 인해 메모리 소자의 programming 시에는 deep trap site에 charging이 일어나고, erasing 시에는 shallow trap site에 캐리어들이 쉽게 공급되면서 deep trap site에 갇혀있던 charge가 쉽게 de-trapped 된다는 장점을 가지고 있다. 따라서, 본 실험에서는 산화물 반도체인 ZnO를 trap layer로 하는 CTF 소자의 메모리 특성을 확인하기 위해 간단한 구조인 metal-oxide capacitor (MOSCAP)구조로 제작하여 메모리 특성을 평가하였다. 먼저, RCA cleaning 처리된 n-Si bulk 기판 위에 tunnel layer인 SiO2 5 nm를 rf sputter로 증착한 후 furnace 장비를 이용하여 forming gas annealing을 $450^{\circ}C$에서 실시하였다. 그 후 ZnO를 20 nm, SiO2를 30 nm rf sputter로 증착한 후, 상부전극을 E-beam evaporator 장비를 사용하여 Al 150 nm를 증착하였다. 제작된 소자의 신뢰성 및 내구성 평가를 위해 상온에서 retention과 endurance 측정을 진행하였다. 상온에서의 endurance 측정결과 1000 cycles에서 약 19.08%의 charge loss를 보였으며, Retention 측정결과, 10년 후 약 33.57%의 charge loss를 보여 좋은 메모리 특성을 가지는 것을 확인하였다. 본 실험 결과를 바탕으로, 차세대 메모리 시장에서 trap layer 물질로 산화물 반도체를 사용하는 CTF의 연구 및 계발, 활용가치가 높을 것으로 기대된다.

• Current Photovoltaic Research
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• v.12 no.2
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• pp.31-36
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• 2024

Passivating contacts are a promising technology for achieving high efficiency Si solar cells by reducing direct metal/Si contact. Among them, a polysilicon (poly-Si) based passivating contact solar cells achieve high passivation quality through a tunnel oxide (SiO_x) and poly-Si. In poly-Si/SiO_x based solar cells, the passivation quality depends on the amount of dopant in-diffused into the bulk-Si. Therefore, our study fabricated cells by inserting silicon oxide (SiO₂) as a doping barrier before doping and analyzed the barrier effect of SiO₂. In the experiments, p⁺ poly-Si was formed using spin on dopant (SOD) method, and samples ware fabricated by controlling formation conditions such as existence of doping barrier and poly-Si thickness. Completed samples were measured using quasi steady state photoconductance (QSSPC). Based on these results, it was confirmed that possibility of achieving high V_oc by inserting a doping barrier even with thin poly-Si. In conclusion, an improvement in implied V_oc of up to approximately 20 mV was achieved compared to results with thicker poly-Si results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.17-21
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• 2009

The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated for nonvolatile memory device applications. The band structure of band-gap engineered tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with the conventional tunneling $SiO_2$ barrier. The band-gap engineered tunneling barriers composed of thin $SiO_2$ and $Si_3N_4$ layers showed a lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.869-875
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• 2017

Using TCAD simulation, performances of tunnel field-effect transistors (TFETs) was investigated. Drain current-gate voltage types of TFET structure such as single-gate TFET (SG-TFET), double-gate TFET (DG-TFET), L-shaped TFET (L-TFET), and Pocket-TFET (P-TFET) are simulated, and then as dielectric constant of gate oxide and channel length are varied their subthreshold swing (SS) and on-current ($I_{on}$) are compared. On-currents and subthreshold swings of the L-TFET and P-TFET structures with high electric constant and line tunneling were 10 times and 20 mV/dec more than those of the SG-TFET and DG-TFET using point tunneling, respectively. Especially, it is shown that hump effect which dominant current element changes from point tunneling to line tunneling, is disappeared in P-TFET with high-k gate oxide such as $HfO_2$. The analysis of 4 types of TFET structure provides guidelines for the design of new types of TFET structure which concentrate on line tunneling by minimizing point tunneling.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.831-837
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• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.128-129
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• 2008

The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.