• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.8.2-8.2
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• 2011

This talk demonstrates diverse patterned structures utilizing in-situ self-organization and phase separation of the materials into an ordered fashion. The patterned structures in this talk include electrospun nanofibers and electrosprayed microparticles embedding small particles. The positions of the small particles are in-situ controlled during the electrohydrodynamic process by the interaction with the polymer matrix. Another topic of the talk includes selective deposition of spin-coated materials on a corrugated surface that was prepared by buckling of polymer thin films. Solution are strong tendency to be positioned in the trench area of the surface, which facilitates the fabrication of micropatterns of diverse materials.

• 한국재료학회지
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• 제16권5호
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• pp.308-311
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• 2006

The purpose of this study is to investigate the difference of the wafer nanotopography impact on the oxide-film thickness variation between the STI CMP using ceria slurry and STI CMP using fumed silica slurry. The nanotopography impact on the oxide-film thickness variation after STI CMP using ceria slurry is 2.8 times higher than that after STI CMP using fumed silica slurry. It is attributed that the STI CMP using ceria slurry follows non-Prestonian polishing behavior while that using fumed silica slurry follows Prestonian polishing behavior.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.95-98
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• 2003

Power semiconductors are being currently used as a application of intelligent power inverters to a refrigerator, a washing machine and a vacuum cleaner as well as core parts of industrial system. The rating of semiconductor devices is an important factor in decision on the field of application and the forward blocking voltage is one of factors in decision of the rating. The Power MOS device has a merit of high input impedance, short switching time, and stability in temperature as well known. Power MOS devices are mainly used as switches in the field of power electronics, especially the on-state resistance and breakdown voltage are regarded as the most important parameters. Power MOS devices that enable a small size, a light weight, high-integration and relatively high voltage are required these days. In this paper, we proposed the new lateral power MOS which has forward blocking voltage of 250V and contains trench electrodes and verified manufactural possibility by using TSUPREM-4 that is process simulator.

• 물과 미래
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• 제19권3호
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• pp.259-266
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• 1986

해저기형 변화가 있는 경우에 파랑의 변형(파의 반사 및 전달계수)을 선형요소를 사용한 경계요소법에 의해 수치해석하였다. 파랑은 2차원 선형파 이론으로부터 해석하였으며, 입사파 방향은 해저바닥상에 임의방향(직각입사 혹은 경사입사)으로 진행한다고 가정하였다. 본 계산의 신뢰도를 검증하기 위하여 다음과 같은 여러 경우에 대한 기존 연구자들의 결과와 비교하였다. (1) 단형이나 경사단락을 가지는 경우 (2) 불투과성 잠제가 있는 경우 (3) 해구가 있는 경우

• ETRI Journal
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• 제35권4호
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• pp.603-609
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• 2013

In this paper, we present a 600-V reverse conducting insulated gate bipolar transistor (RC-IGBT) for soft and hard switching applications, such as general purpose inverters. The newly developed RC-IGBT uses the deep reactive-ion etching trench technology without the thin wafer process technology. Therefore, a freewheeling diode (FWD) is monolithically integrated in an IGBT chip. The proposed RC-IGBT operates as an IGBT in forward conducting mode and as an FWD in reverse conducting mode. Also, to avoid the destructive failure of the gate oxide under the surge current and abnormal conditions, a protective Zener diode is successfully integrated in the gate electrode without compromising the operation performance of the IGBT.

• 한국시뮬레이션학회논문지
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• 제11권1호
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• pp.23-30
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• 2002

An STI(Shallow Trench Isolation) by using a CMP(Chemical Mechanical Polishing) process has been one of the key issues in the device isolation[1] In this paper we fabricated N, P-MOSFEET tall analyse hump characteristics in various rounding oxdation thickness(ex : Skip, 500, 800, 1000$\AA$). As a result we found that hump occurred at STI channel edge region by field oxide recess. and boron segregation(early turn on due to boron segregatiorn at channel edge). Therefore we improved that hump occurrence by increased oxidation thickness, and control field oxide recess( 20nm), wet oxidation etch time(19HF,30sec), STI nitride wet cleaning time(99HF, 60sec+P 90min) and fate pre-oxidation cleaning time (U10min+19HF, 60sec) to prevent hump occurring at STI channel edge.

• 한국표면공학회지
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• 제38권1호
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• pp.28-36
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• 2005

In this study, the reflow characteristics of copper thin films which is expected to be used as interconnection materials in the next generation semiconductor devices were investigated. Cu thin films were deposited on the TaN diffusion barrier by metal organic chemical vapor deposition (MOCVD) and annealed at the temperature between 250℃ and 550℃ in various ambient gases. When the Cu thin films were annealed in the hydrogen ambience compared with oxygen ambience, sheet resistance of Cu thin films decreased and the breakdown of TaN diffusion barrier was not occurred and a stable Cu/TaN/Si structure was formed at the annealing temperature of 450℃. In addition, reflow properties of Cu thin films could be enhanced in H₂ ambient. With Cu reflow process, we could fill the trench patterns of 0.16～0.24 11m with aspect ratio of 4.17～6.25 at the annealing temperature of 450℃ in hydrogen ambience. It is expected that Cu reflow process will be applied to fill the deep pattern with ultra fine structure in metallization.

• 센서학회지
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• 제15권5호
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• pp.341-346
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• 2006

We have fabricated SOI CMOS active pixel image sensor with the pinned photodiode on handle wafer in order to reduce dark currents and improve spectral response. The structure of the active pixel image sensor is 4 transistors APS which consists of a reset and source follower transistor on seed wafer, and is comprised of the photodiode, transfer gate, and floating diffusion on handle wafer. The source of dark current caused by the interface traps located on the surface of a photodiode is able to be eliminated, as we apply the pinned photodiode. The source of dark currents between shallow trench isolation and the depletion region of a photodiode can be also eliminated by the planner process of the hybrid bulk/SOI structure. The photodiode could be optimized for better spectral response because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. The dark current was about 6 pA at 3.3 V of floating diffusion voltage in the case of transfer gate TX = 0 V and TX=3.3 V, respectively. The spectral response of the pinned photodiode was observed flat in the wavelength range from green to red.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.117-118
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• 2008

High-pressure deuterium annealing process is proposed and investigated for enhanced electrical and reliability properties of 512Mb DDR2 DRAM without increase in process complexity. High pressure deuterium annealing (HPDA) introduced during post metal anneal (PMA) improves not only DRAM performance but also reliability characteristics of MOSFET. Compared with a control sample annealed in a conventional forming gas, additional annealing in a high pressure deuterium ambient at $400^{\circ}C$ for 30 min decreased G1DL current and junction leakage. The improvements can be explained by deuterium incorporation at $SiO_2$/Si substrate interface near isolation trench edge.

• 한국지형학회지
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• 제15권2호
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• pp.67-83
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• 2008

아산 지역에 있어서 최종빙기 최성기 이후 구릉사면의 삭박과정을 밝히기 위하여 매곡천 하류부에 위치한 '아골'의 곡저에서 트렌치 작업을 행하여 채취한 분석시료를 대상으로 층상해석과 탄소연대 측정을 실시하였다. 그 결과는 다음과 같다. 조사지역의 트렌치 MG1, MG2, MG3 지점에서 무기물층과 유기물층은 각각 11매와 8매, 7매와 3매, 5매와 3매가 확인되었다. MG1 지점에서 배후 구릉사면의 불안정한 환경하에 발생했던 사면삭박 즉, 사면물질이동은 총 11회 (약 2,900yrBP 이전에 8회, 약 2,900~1,900yrBP 사이에 2회, 약 1,900yrBP 이후에 1회)이다. 그리고 상대적으로 배후 구릉사면의 안정된 환경하에서 형성된 저습지의 횟수는 최소 총 9회(약 3,000yrBP이전에 5회, 약 3,000~2,800yrBP 사이에 2회, 약 2,200~1,900yrBP 사이에 1회)이다. MG2 지점에서 배후 구릉사면의 삭박은 총 7회(약 1,900yrBP이전에 4회, 약 1,900yrBP 이후에 3회)이고, 저습지의 형성은 총 3회(약 1,900yrBP이전에 2회, 약 1,900yrBP 이후에 1회)이다. MG3 지점에서 배후 구릉사면의 삭박 횟수는 총 5회(약 1,900yrBP이전 3회, 약 1,900yrBP 이후에 2회)이고, 저습지의 형성은 총 3회(약 1,900yrBP 이전에 2회, 약 1,900yrBP 이후에 1회)이다. 따라서 아골 곡저를 둘러싼 구릉사면은 1회가 아닌 수 회의 삭박에 의해 형성되었으며, 다양한 유형의 무기물질이 토사류 또는 토석류와 같은 사면물질이동에 의해 조사지역의 곡저에 매적된 것으로 밝혀졌다. 그리고 구릉사면의 삭박주기는 약 $10^2{\sim}10^3$년 시간규모에 수렴되는 것도 알 수 있었다. 이 결과는 아산 주변에 분포하는 구릉사면의 삭박과정 및 제4기 후기의 기후변화 복원에 중요한 기초자료가 될 것이다.