• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.339-341
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• 1997

From this first studies, We have investigated the latch-up characteristics of various CMOS well structures possible with high energy ion implantation processes. In this study, we also investigated those of STI(Shallow Trench Isolation} structures with varing n+/p+ spacing and the depth of trench. STI structure is formed by T-SUPREM4 process simulator, and then latch-up simulations for each case were performed by MEDICI device simulator for latch-up immunity improvement. STI is very effective to preventing the degradation of latch-up characteristics as the n+/p+ spacing is reduced. These studies will allow us to evaluate each technology and suggest guidelines for the optimization of latch-up susceptibility.

• Transactions on Electrical and Electronic Materials
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• v.10 no.6
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• pp.189-192
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• 2009

The leakage current in a CMOS image sensor (CIS) can have various origins. Leakage current investigations have focused on such things as cobalt-salicide, source and drain scheme, and shallow trench isolation (STI) profile. However, there have been few papers examining the effects on leakage current of nitride stringers that are formed by gate sidewall etching. So this study reports the results of a series of experiments on the effects of a nitride stringer on real display images. Different step heights were fabricated during a STI chemical mechanical polishing process to form different nitride stringer sizes, arsenic and boron were implanted in each fabricated photodiode, and the doping density profiles were analyzed. Electrons that moved onto the silicon surface caused the dark leakage current, which in turn brought up the speckle defect on the display image in the CIS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.759-762
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• 2000

Present transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area, consequently have disadvantage for high speed switching performance. In this paper, a horizontal structure transistor which has minimized parasitic capacitance in virtue of SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics were designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance was proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed horizontal structure transistor was certified through the VCE-lC characteristics curve, $h_{FE}$ -IC characteristics, and GP-plot.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.11a
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• pp.87-88
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• 2007

무전해 구리 도금 공정에서 첨가제로 사용되는 HIQSA 화합물이 Damascene 공정을 이용한 60nm급 trench 패턴 내 무전해 구리 배선 형성 과정에 미치는 효과를 전기 화학적 기법과 광학적 기법을 이용하여 관찰하였다. HIQSA 농도별 open circuit potential의 변화를 관측한 결과, 3ppm 수준으로 첨가되었을 때, 무전해 도금 과정 중 가장 안정한 전위가 유지됨을 볼 수 있었다. 무전해 도금액 내 HIQSA 농도가 높아짐에 따라 구리 도금층의 두께는 지수적으로 감소하였으며, 표면의 결정 크기도 감소하였다. 60nm급 trench 내 무전해 구리 도금 시, 용액 내 침적 시간 60초가 무결함 superconformal copper filling을 얻기 위한 최적 시간이었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.3
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• pp.203-207
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• 2008

Chemical mechanical polishing (CMP) allows the planarization of wafers with two or more materials. There are many elements such as slurry, polishing pad, process parameters and conditioning in CMP process. Especially, polishing pad is considered as one of the most important consumables because this affects its performances such as WIWNU(within wafer non-uniformity) and MRR(material removal rate). In polishing pad, grooves and pores on its surface affect distribution of slurry, flow and profile of MRR on wafer. A subject of this investigation is to apply CMP for planarization of shallow trench isolation structure using microstructure(MS) pad. MS pad is designed to have uniform structure on its surface and manufactured by micro-molding technology. And then STI CMP performances such as pattern selectivity, erosion and comer rounding are evaluated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.68-68
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• 2011

As feature size is smaller, new technology are needed in semiconductor factory such as gap-fill technology for sub 100nm, development of ALD equipment for Cu barrier/seed, oxide trench etcher technology for 25 nm and beyond, development of high throughput Cu CMP equipment for 30nm and development of poly etcher for 25 nm and so on. We are focus on gap-fill technology for sub-30nm. There are many problems, which are leaning, over-hang, void, micro-pore, delaminate, thickness limitation, squeeze-in, squeeze-out and thinning phenomenon in sub-30 nm gap fill. New gap-fill processes, which are viscous oxide-SOD (spin on dielectric), O3-TEOS, NF3 Based HDP and Flowable oxide have been attempting to overcome these problems. Some groups investigated SOD process. Because gap-fill performance of SOD is best and process parameter is simple. Nevertheless these advantages, SOD processes have some problems. First, material cost is high. Second, density of SOD is too low. Therefore annealing and curing process certainly necessary to get hard density film. On the other hand, film density by Flowable oxide process is higher than film density by SOD process. Therefore, we are focus on Flowable oxide. In this work, dielectric film were deposited by PECVD with TSA(Trisilylamine - N(SiH3)3) and NH3. To get flow-ability, the effect of plasma treatment was investigated as function of O2 plasma power. QMS (quadruple mass spectrometry) and FTIR was used to analysis mechanism. Gap-filling performance and flow ability was confirmed by various patterns.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.41 no.6
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• pp.423-427
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• 2017

In this paper, an anchor design that improves bonding strength uniformity in the silicon-on-glass (SOG) process is presented. The SOG process is widely used in conjunction with electrode-patterned glass substrates as a standard fabrication process for forming high-aspect-ratio movable silicon microstructures in various types of sensors, including inertial and resonant sensors. In the proposed anchor design, a trench separates the silicon-bonded area and the electrode contact area to prevent irregular bonding caused by the protrusion of the electrode layer beyond the glass surface. This technique can be conveniently adopted to almost all devices fabricated by the SOG process without the necessity of additional processes.

• Korean Journal of Materials Research
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• v.13 no.5
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• pp.333-337
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• 2003

We report a new fabrication process for carbon nanotube field emitters with high performance. The key of the fabrication process is trim-and-leveling the carbon nanotubes grown in trench structures by employing a planarization process, which leads to a uniform distance from the carbon nanotube tip to the electrode. In order to enable this processing, spin-on-glass liquid is applied over the CNTs grown in trench to have them stubborn adhesion among themselves as well as to the substrate. Thus fabricated emitters reveal an extremely stable emission and aging characteristics with a large current density of 40 ㎃/$\textrm{cm}^2$ at 4.5 V/$\mu\textrm{m}$. The field enhancement factor calculated from the F-N plot is $1.83${\times}$10^{5}$ $cm^{－1}$ , which is a very high value and indicates a superior quality of the emitter originating from the nature of open-tip and high stability of the carbon nanotubes obtained new process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.14-17
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• 2000

The rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STi CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. We studied the current sensing method in STI-CMP with the reverse moat pattern.