Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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Investigations of Latch-up characteristics of CMOS well structure with STI technology

STI 기술을 채용한 CMOS well 구조에서의 Latch-up 특성 평가

  • Kim, In-Soo (Dept. of Electrical Engineering, Korea University) ;
  • Kim, Chang-Duk (Dept. of Electrical Engineering, Korea University) ;
  • Kim, Jong-Chul (Dept. of Electrical Engineering, Korea University) ;
  • Kim, Jong-Kwan (Dept. of Electrical Engineering, Korea University) ;
  • Sung, Yung-Kwon (Dept. of Electrical Engineering, Korea University)
  • 김인수 (고려대학교 전기전자전파 공학부) ;
  • 김창덕 (고려대학교 전기전자전파 공학부) ;
  • 김종철 (고려대학교 전기전자전파 공학부) ;
  • 김종관 (고려대학교 전기전자전파 공학부) ;
  • 성영권 (고려대학교 전기전자전파 공학부)
  • Published : 1997.11.29
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Abstract

From this first studies, We have investigated the latch-up characteristics of various CMOS well structures possible with high energy ion implantation processes. In this study, we also investigated those of STI(Shallow Trench Isolation} structures with varing n+/p+ spacing and the depth of trench. STI structure is formed by T-SUPREM4 process simulator, and then latch-up simulations for each case were performed by MEDICI device simulator for latch-up immunity improvement. STI is very effective to preventing the degradation of latch-up characteristics as the n+/p+ spacing is reduced. These studies will allow us to evaluate each technology and suggest guidelines for the optimization of latch-up susceptibility.

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