• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.10
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• pp.720-725
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• 2013

Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have analyzed trench process, field limit ring process for fabrication of unified trench gate power MOSFET. And we have analyzed electrical characteristics of fabricated unified trench gate power MOSFET. The optimal trench process was based on SF6. After we carried out SEM measurement, we obtained superior trench gate and field limit ring process. And we compared electrical characteristics of planar and trench gate unified power MOSFET after completing device fabrication. As a result, the both of them was obtained 500 V breakdown voltage. However trench gate unified power MOSFET was shown improved Vth and on state voltage drop characteristics than planar gate unified power MOSFET.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.118-119
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• 2009

This paper presents the feature profile evolution silicon deep trench etching, which is very crucial for the commercial wafer process application. The silicon deep trenches were etched with the SF6 gas & Hbr gas based process recipe. The optimized silicon deep trench process resulted in vertical profiles (87o~90o) with loading effect of < 1%. The process recipes were developed for the silicon deep trench etching applications. This scheme provides vertically profiles without notching of top corner was observed. In this study, the production of SF6 gas based silicon deep trench etch process much more strongly than expected on the basis of Hbr gas trench process that have been investigated by scanning electron microscope (SEM). Based on the test results, it is concluded that the silicon deep trench etching shows the sufficient profile for practical MOS FET silicon deep trench technology process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.88-89
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• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

• Journal of IKEEE
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• v.22 no.4
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• pp.1234-1237
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• 2018

For 4H-SiC trench MOSFET which can reduce on-resistance and switching losses compared to 4H-SiC planar MOSFET, the optimization study for decrease of sub-trench was carried out. In order to decrease sub-trench, Ar reshape process was used and trench shapes were observed as a function of temperature and process time. As a result, it was confirmed that the process conditions for $1500^{\circ}C$ and 20 min were most effective for the suitable trench profiles. In addition, dry/wet oxidation was performed at the Ar reshaped-samples to observe the oxidation thickness with different crystal orientations.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.9
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• pp.438-443
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• 2001

In the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control, within-wafer-non-uniformity, and the possible defects such as pad oxide damage and nitride residue. The defect like nitride residue and silicon (or pad oxide) damage after STI-CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI fill and STI-CMP were discussed. Consequently, we could conclude that law trench depth and high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.501-504
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• 1999

In the shallow trench isolation(STI) chemical mechanical polishing(CMP) process, the key issues are the optimized thickness control within- wafer-non-uniformity, and the possible defects such as nitride residue and pad oxide damage. These defects after STI CMP process were discussed to accomplish its optimum process condition. To understand its optimum process condition, overall STI related processes including reverse moat etch, trench etch, STI filling and STI CMP were discussed. It is represented that the nitride residue can be occurred in the condition of high post CMP thickness and low trench depth. In addition there are remaining oxide on the moat surface after reverse moat etch. It means that reverse moat etching process can be the main source of nitride residue. Pad oxide damage can be caused by over-polishing and high trench depth.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.843-847
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• 2014

In Super Junction (SJ) MOSFETs, charge balance is the most important issue of the SJ fabrication process. In order to achieve the best electrical characteristics, such as breakdown voltage and on-resistance, the N-type and P-type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, which is known as the charge balance condition. In conventional charge balance analysis, based on multi-epi process SJ MOSFETs, analytical model has only N, P pillar width and doping concentration parameter. But applying a conventional charge balance principle to trench filling process, easier than Multi-epi process, is impossible due to the missing of the trench angle parameter. To achieve much more superior characteristics of on-resistance in trench filling SJ MOFET, the appropriate trench angle is necessary. So in this paper, modulated charge balance analysis is proposed, in which a trench angle parameter is added. The proposed method is validated using the TCAD simulation tool.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.964-969
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• 2014

In Super Junction MOSFET, Charge Balance is the most important issue of the trench filling Super Junction fabrication process. In order to achieve the best electrical characteristics, the N type and P type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, called Charge Balance Condition. In this paper, two methods from the fabrication process were used at the Charge Balance condition: Trench angle decreasing process and Bottom implantation process. A lower on-resistance could be achieved using a lower trench angle. And a higher breakdown voltage could be achieved using the bottom implantation process. The electrical characteristics of manufactured discrete device chips are compared with those of the devices which are designed of TCAD simulation.

• Journal of IKEEE
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• v.25 no.2
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• pp.356-361
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• 2021

Super Junction structure is the proposed structure to minimize the Trade-off phenomenon of power devices. Super Junction can have On-resistance(Ron) characteristics as less as five times than conventional structure. There are process methods that Multi-Epi and Deep-Trench of Super Junction structure. The reason for this is that Deep-Trench process is known to be a relatively difficult manufacturing method because it is easy to form a P-Pillar by burying impurities on top of a silicon substrate through a Deep-Trench process. However, the structure created by the Deep-Trench process has low On-resistance and high breakdown voltage, showing better efficiency. In this paper, we suggested a novel method in the process and designed structure with Charge Balance theory.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.17-23
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• 2002

The more productive and stable fabrication can be obtained by applying chemical mechanical polishing (CMP) process to shallow trench isolation (STI) structure in 0.18 $\mu\textrm{m}$ semiconductor device. However, STI-CMP process became more complex, and some kinds of defect such as nitride residue, tern oxide defect were seriously increased. Defects like nitride residue and silicon damage after STI-CMP process were discussed to accomplish its optimum process condition. In this paper, we studied how to reduce torn oxide defects and nitride residue after STI-CMP process. To understand its optimum process condition, We studied overall STI-related processes including trench depth, STI-fill thickness and post-CMP thickness. As an experimental result showed that as the STI-fill thickness becomes thinner, and trench depth gets deeper, more tern oxide were found in the CMP process. Also, we could conclude that low trench depth whereas high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.