• Title/Summary/Keyword: Trap Density

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Improvement of the carrier transport property and interfacial behavior in InGaAs quantum well Metal-Oxide-Semiconductor Field-Effect-Transistors with sulfur passivation (황화 암모늄을 이용한 Al2O3/HfO2 다층 게이트 절연막 트랜지스터 전기적 및 계면적 특성 향상 연구)

  • Kim, Jun-Gyu;Kim, Dae-Hyun
    • Journal of Sensor Science and Technology
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    • v.29 no.4
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    • pp.266-269
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    • 2020
  • In this study, we investigated the effect of a sulfur passivation (S-passivation) process step on the electrical properties of surface-channel In0.7Ga0.3As quantum-well (QW) metal-oxide-semiconductor field-effect transistors (MOSFETs) with S/D regrowth contacts. We fabricated long-channel In0.7Ga0.3As QW MOSFETs with and without (NH4)2S treatment and then deposited 1/4 nm of Al2O3/HfO2 through atomic layer deposition. The devices with S-passivation exhibited lower values of subthreshold swing (74 mV/decade) and drain-induced barrier lowering (19 mV/V) than the devices without S-passivation. A conductance method was applied, and a low value of interface trap density Dit (2.83×1012 cm-2eV-1) was obtained for the devices with S-passivation. Based on these results, interface traps between InGaAs and high-κ are other defect sources that need to be considered in future studies to improve III-V microsensor sensing platforms.

Effect of SiO2 Buffer Layer Thickness on the Device Reliability of the Amorphous InGaZnO Pseudo-MOS Field Effect Transistor (SiO2 완충층 두께에 따른 비정질 InGaZnO Pseudo-MOS Field Effect Transistor의 신뢰성 평가)

  • Lee, Se-Won;Hwang, Yeong-Hyeon;Cho, Won-Ju
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.1
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    • pp.24-28
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    • 2012
  • In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.

A study on Improvement of sub 0.1$\mu\textrm{m}$VLSI CMOS device Ultra Thin Gate Oxide Quality Using Novel STI Structure (STI를 이용한 서브 0.1$\mu\textrm{m}$VLSI CMOS 소자에서의 초박막게이트산화막의 박막개선에 관한 연구)

  • 엄금용;오환술
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.9
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    • pp.729-734
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    • 2000
  • Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

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DC magnetron sputtering을 이용하여 증착한 $SnO_2$ 기반의 박막 트랜지스터의 전기적 및 광학적 특성 비교

  • Kim, Gyeong-Taek;Mun, Yeon-Geon;Kim, Ung-Seon;Sin, Sae-Yeong;Park, Jong-Wan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.08a
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    • pp.104-104
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    • 2010
  • 현재 디스플레이 시장은 급변하게 변화하고 있다. 특히, 비정질 실리콘의 경우 디스플레이의 채널층으로 주로 상용화되어 왔다. 비정질 실리콘 기반의 박막 트랜지스터는 제작의 경제성 및 균일성을 가지고 있어서 널리 상용화되고 있다. 하지만 비정질 실리콘의 경우 낮은 전자 이동도(< $1\;cm^2/Vs$)로 인하여 디스플레이의 대면적화에 부적합하며, 광학적으로 불투명한 특성을 갖기 때문에 차세대 디스플레이의 응용에 불리한 점이 있다. 이런 문제점의 대안으로 현재 국내외 여러 연구 그룹에서 산화물 기반의 반도체를 박막 트랜지스터의 채널층으로 사용하려는 연구가 진행중이다. 산화물 기반의 반도체는 밴드갭이 넓어서 광학적으로 투명하고, 상온에서 증착이 가능하며, 비정질 실리콘에 비해 월등히 우수한 이동도를 가짐으로 디스플레이의 대면적화에 유리하다. 특히 Zinc Oxide, Tin Oxide, Titanum Oxide등의 산화물이 연구되고 있으며, indium이나 aluminum등을 첨가하여 전기적인 특성을 향상시키려는 노력을 보이고 있다. Tin oxide의 경우 천연적으로 풍부한 자원이며, 낮은 가격이 큰 이점으로 작용을 한다. 또한, $SnO_2$의 경우 ITO나 ZnO 열적으로 화학적 과정에서 더 안정하다고 알려져 있다. 본 연구에서는 $SnO_2$ 기반의 박막 트랜지스터를 DC magnetron sputtering를 이용하여 상온에서 제작을 하였다. 일반적으로, $SnO_2$의 경우 증착 과정에서 산소 분압 조절과 oxygen vacancy 조절를 통하여 박막의 전도성을 조절할 수 있다. 이렇게 제작된 $SnO_2$의 박막을 High-resolution X-ray diffractometer, photoluminescence spectra, Hall effect measurement를 이용하여 전기적 및 광학적 특성을 알 수 있다. 그리고 후열처리 통하여 박막의 전기적 특성 변화를 확인하였다. gate insulator의 처리를 통하여 thin film의 interface의 trap density를 감소시킴으로써 소자의 성능 향상을 시도하였다. 그리고 semiconductor analyzer로 소자의 출력 특성 및 전이 특성을 평가하였다. 그리고 Temperature, Bias Temperature stability, 경시변화 등의 다양한 조건에서의 안정성을 평가하여 안정성이 확보된다면 비정질 실리콘을 대체할 유력한 후보 중의 하나가 될 것이라고 기대된다.

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Performance Improvement of All Solution Processable Organic Thin Film Transistors by Newly Approached High Vacuum Seasoning

  • Kim, Dong-Woo;Kim, Hyoung-Jin;Lee, Young-Uk;Hong, Mun-Pyo
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.470-470
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    • 2012
  • Organic thin film transistors (OTFTs) backplane constitute the active elements in new generations of plastic electronic devices for flexible display. The overall OTFTs performance is largely depended on the properties and quality of each layers of device material. In solution based process of organic semiconductors (OSCs), the interface state is most impediments to preferable performance. Generally, a threshold voltage (Vth) shift is usually exhibited when organic gate insulators (OGIs) are exposed in an ambient air condition. This phenomenon was caused by the absorbed polar components (i.e. oxygen and moisture) on the interface between OGIs and Soluble OSCs during the jetting process. For eliminating the polar component at the interface of OGI, the role of high vacuum seasoning on an OGI for all solution processable OTFTs were studied. Poly 4-vinly phenols (PVPs) were the material chosen as the organic gate dielectric, with a weakness in ambient air. The high vacuum seasoning of PVP's surface showed improved performance from non-seasoning TFT; a $V_{th}$, a ${\mu}_{fe}$ and a interface charge trap density from -8V, $0.018cm^2V^{-1}s^{-1}$, $1.12{\times}10^{-12}(cm^2eV)^{-1}$ to -4.02 V, $0.021cm^2V^{-1}s^{-1}$, $6.62{\times}10^{-11}(cm^2eV)^{-1}$. These results of OTFT device show that polar components were well eliminated by the high vacuum seasoning processes.

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Effect of Negative Oxygen Ions Accelerated by Self-bias on Amorphous InGaZnO Thin Film Transistors

  • Kim, Du-Hyeon;Yun, Su-Bok;Hong, Mun-Pyo
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.466-468
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    • 2012
  • Amorphous InGaZnO (${\alpha}$-IGZO) thin-film transistors (TFTs) are are very promising due to their potential use in thin film electronics and display drivers [1]. However, the stability of AOS-TFTs under the various stresses has been issued for the practical AOSs applications [2]. Up to now, many researchers have studied to understand the sub-gap density of states (DOS) as the root cause of instability [3]. Nomura et al. reported that these deep defects are located in the surface layer of the ${\alpha}$-IGZO channel [4]. Also, Kim et al. reported that the interfacial traps can be affected by different RF-power during RF magnetron sputtering process [5]. It is well known that these trap states can influence on the performances and stabilities of ${\alpha}$-IGZO TFTs. Nevertheless, it has not been reported how these defect states are created during conventional RF magnetron sputtering. In general, during conventional RF magnetron sputtering process, negative oxygen ions (NOI) can be generated by electron attachment in oxygen atom near target surface and accelerated up to few hundreds eV by self-bias of RF magnetron sputter; the high energy bombardment of NOIs generates bulk defects in oxide thin films [6-10] and can change the defect states of ${\alpha}$-IGZO thin film. In this paper, we have confirmed that the NOIs accelerated by the self-bias were one of the dominant causes of instability in ${\alpha}$-IGZO TFTs when the channel layer was deposited by conventional RF magnetron sputtering system. Finally, we will introduce our novel technology named as Magnetic Field Shielded Sputtering (MFSS) process [9-10] to eliminate the NOI bombardment effects and present how much to be improved the instability of ${\alpha}$-IGZO TFTs by this new deposition method.

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Electron Trapping and Transport in Poly(tetraphenyl)silole Siloxane of Quantum Well Structure

  • Choi, Jin-Kyu;Jang, Seung-Hyun;Kim, Ki-Jeong;Sohn, Hong-Lae;Jeong, Hyun-Dam
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.158-158
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    • 2012
  • A new kind of organic-inorganic hybrid polymer, poly(tetraphenyl)silole siloxane (PSS), was invented and synthesized for realization of its unique charge trap properties. The organic portions consisting of (tetraphenyl)silole rings are responsible for electron trapping owing to their low-lying LUMO, while the Si-O-Si inorganic linkages of high HOMO-LUMO gap provide the intrachain energy barrier for controlling electron transport. Such an alternation of the organic and inorganic moieties in a polymer may give an interesting quantum well electronic structure in a molecule. The PSS thin film was fabricated by spin-coating of the PSS solution in THF organic solvent onto Si-wafer substrates and curing. The electron trapping of the PSS thin films was confirmed by the capacitance-voltage (C-V) measurements performed within the metal-insulator-semiconductor (MIS) device structure. And the quantum well electronic structure of the PSS thin film, which was thought to be the origin of the electron trapping, was investigated by a combination of theoretical and experimental methods: density functional theory (DFT) calculations in Gaussian03 package and spectroscopic techniques such as near edge X-ray absorption fine structure spectroscopy (NEXAFS) and photoemission spectroscopy (PES). The electron trapping properties of the PSS thin film of quantum well structure are closely related to intra- and inter-polymer chain electron transports. Among them, the intra-chain electron transport was theoretically studied using the Atomistix Toolkit (ATK) software based on the non-equilibrium Green's function (NEGF) method in conjunction with the DFT.

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Passivation Effects of Excimer-Laser-Induced Fluorine using $SiO_{x}F_{y}$ Pad Layer on Electrical Characteristics and Stability of Poly-Si TFTs ($SiO_{x}F_{y}$/a-Si 구조에 엑시머 레이저 조사에 의해 불소화된 다결정 실리콘 박막 트랜지스터의 전기적 특성과 신뢰도 향상)

  • Kim, Cheon-Hong;Jeon, Jae-Hong;Yu, Jun-Seok;Han, Min-Gu
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.48 no.9
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    • pp.623-627
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    • 1999
  • We report a new in-situ fluorine passivation method without in implantation by employing excimer laser annealing of $SiO_{x}F_{y}$/a-Si structure and its effects on p-channel poly-Si TFTs. The proposed method doesn't require any additional annealing step and is a low temperature process because fluorine passivation is simultaneous with excimer-laser-induced crystallization. A in-situ fluorine passivation by the proposed method was verified form XPS analysis and conductivity measurement. From experimental results, it has been shown that the proposed method is effective to improve the electrical characteristics, specially field-effect mobility, and the electrical stability of p-channel poly-Si TFTs. The improvement id due to fluorine passivation, which reduces the trap state density and forms the strong Si-F bonds in poly-Si channel and $SiO_2/poly-Si$ interface. From these results, the high performance poly-Si TFTs canbe obtained by employing the excimer-laser-induced fluorine passivation method.

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A Study on the Characteristic of MOS structure using $HfO_{2}$ as high-k gate dielectric film ($HfO_{2}$를 이용한 MOS 구조의 제작 및 특성)

  • Park, C.I.;Youm, M.S.;Park, J.W.;Kim, J.W.;Sung, M.Y.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.11a
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    • pp.163-166
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    • 2002
  • We investigated structural and electrical properties of Metal-Oxide-Semiconductor(MOS) structure using Hafnium $oxide(HfO_{2})$ as high-k gate dielectric material. $HfO_{2}$ films are ultrathin gate dielectric material witch have a thickness less than 2.0nm, so it is spotlighted to be substituted $SiO_{2}$ as gate dielectric material. In this paper We have grown $HfO_{2}$ films with pt electrode on P-type Silicon substrate by RF magnetron sputtering system using $HfO_{2}$ target and oserved the property of semiconductor-oxide interface. Using pt electrode, it is necessary to be annealed at ${300^{\circ}C}$. This process is to increase an adhesion ratio between $HfO_{2}$ films with pt electrode. In film deposition process, the deposition time of $HfO_{2}$ films is an important parameter. Structura1 properties are invetigated by AES depth profile, and electrical properties by Capacitance-Voltage characteristic. Interface trap density are measured to observe the interface between $HfO_{2}$ with Si using High-frequency(1MHz) C-V and Quasi - static C-V characteristic.

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Studies on Community and Seasonal Occurrence of chigger Mites around Yedang lake (예당지 주변의 털진드기류 군집 조사)

  • 강병찬;김명해
    • The Korean Journal of Ecology
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    • v.21 no.1
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    • pp.97-103
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    • 1998
  • Yedang lake has so plentiful pondage and many species of fresh-walter-fish that a large number of people crowd around there all the year round. Most of them are not used to prevent tsutsugamushi disease spreading by chigger(T-mite). Accordingly, this study was carried out in order to obtain basic materials for prevention of this disease and the results are summarized as follows. The number of wild rat that captured in surveyed areas was sixty five(apodemus agrarius: 63, Rattus norvegicus: 2) during the period of a year and ration of captured rats to trap was about 8%. The dominant species of T-mite in all the surveyed areas were Leptotrombidium pallidum and L. palpale and the total number collected was 5782.9 with one family, two genra, eight species. The density of T-mites that collected from rats in three areas(Nodongri, Hatanbangri, Kyochonri) appeared $743.3{\pm}80.4,\;847.2{\pm}86.2\;and\;869.6{\pm}86.4,\;and\;in\;soil\;149.5{\pm}13.9,;154.7{\pm}14.7\;and\;182.4{\pm}20.8$ respectively. On the whole, the number of T-mite that collected from the rats was about three times as much as it in soil. The comparison of individual number of T-mite per a rat collected in three surveyed sites(A,B and C) showed 126.7, 243.1, 258.6 and per $2,000cm^3$ of soil 12.7, 12.7, 54.6, 103.5 respectively. In other word, the number of T-mite at site A and B is smaller than that at area C, thus comparing habitats of three sites each other, C is better living environment of rat and mite than that of A or B. Seasonl occuarance of t-mite that is from rat gradually was increased toward winter and showed the peak to January, and decreased since March but it in soil was inverse proportion to it from rats, because the larvae of T-mite that was hatched in soil was transmited to host in order to suck the body fluid.

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