Journal of Sensor Science and Technology (센서학회지)

The Korean Sensors Society (한국센서학회)
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Improvement of the carrier transport property and interfacial behavior in InGaAs quantum well Metal-Oxide-Semiconductor Field-Effect-Transistors with sulfur passivation

황화 암모늄을 이용한 Al2O3/HfO2 다층 게이트 절연막 트랜지스터 전기적 및 계면적 특성 향상 연구

  • Kim, Jun-Gyu (School of Electronics Engineering, Kyungpook National Unversity) ;
  • Kim, Dae-Hyun (School of Electronics Engineering, Kyungpook National Unversity)
  • 김준규 (경북대학교 전자공학부) ;
  • 김대현 (경북대학교 전자공학부)
  • Received : 2020.07.21
  • Accepted : 2020.07.31
  • Published : 2020.07.31
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Abstract

In this study, we investigated the effect of a sulfur passivation (S-passivation) process step on the electrical properties of surface-channel In0.7Ga0.3As quantum-well (QW) metal-oxide-semiconductor field-effect transistors (MOSFETs) with S/D regrowth contacts. We fabricated long-channel In0.7Ga0.3As QW MOSFETs with and without (NH4)2S treatment and then deposited 1/4 nm of Al2O3/HfO2 through atomic layer deposition. The devices with S-passivation exhibited lower values of subthreshold swing (74 mV/decade) and drain-induced barrier lowering (19 mV/V) than the devices without S-passivation. A conductance method was applied, and a low value of interface trap density Dit (2.83×1012 cm-2eV-1) was obtained for the devices with S-passivation. Based on these results, interface traps between InGaAs and high-κ are other defect sources that need to be considered in future studies to improve III-V microsensor sensing platforms.

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References

  1. J. A. del Alamo, X. Cai, J. Lin, W. Lu, A. Vardi, and X. Zhao, "CMOS beyond Si: Nanometer-Scale III-V MOSFETs", 2017 IEEE Bipolar/BiCMOS Circuits Technol. Meet., pp. 26-29, Florida, United States, 2017.
  2. H. Tseng, Y. Fang, S. Zhong, and M. J. W. Rodwell, "InP MOSFETs Exhibiting Record 70 mV/dec Subthreshold Swing", 2019 Device Res. Conf., pp. 183-184, University of Michigan, United States, 2019.
  3. C. B. Zota, C. Convertino, Y. Baumgartner, M. Sousa, D. Caimi, and L. Czornomaz, "High Performance Quantum Well InGaAs-On-Si MOSFETs With sub-20 nm Gate Length For RF Applications", 2018 IEEE Int. Electron Devices Meet., pp. 39.4.1-39.4.4, San Francisco, United States, 2018.
  4. M. Yokoyama, N. Taoka, R. Suzuki, O. Ichikawa, H. Yamada, N. Fukuhara, M. Hata, M. Sugiyama, Y. Nakano, M. Takenaka, and S. Takagi, "Sulfur cleaning for (100), (111)A, and (111)B InGaAs surfaces with In content of 0.53 and 0.70 and their Al2O3/InGaAs MOS interface properties", 2012 Int. Conf. on Indium Phosphide and Relat. Mater., pp. 167-170, Santa Barbara, United States, 2012.
  5. F. Xue, A. Jiang, H. Zhao, Y.-T. Chen, Y. Wang, F. Zhou, and J. Lee, "Channel Thickness Dependence of InGaAs Quantum-Well Field-Effect Transistors With High- k Gate Dielectrics", IEEE Electron Device Lett., Vol. 33, No. 9, pp. 1255-1257, 2012. https://doi.org/10.1109/LED.2012.2205214
  6. S. Guha, V. Narayanan, V. Paruchuri, B. Linder, M. Copel, N. Bojarczuk, Y.-H. Kim, M. Chudzik, Y. Wang, P. Ronsheim, and E. Cartier, "Effects of gate-last and gate-first process on deep submicron inversion-mode InGaAs n-channel metal-oxide-semiconductor field effect transistors", J. Appl. Phys., Vol. 109, No. 5, pp. 053709(1)-053709(6), 2011. https://doi.org/10.1063/1.3553440
  7. S. Guha et al., "Charge Defects, Vt Shifts, and the Solution to the High-K Metal Gate n-MOSFET Problem," in ECS Transactions, 2006, Vol. 3, pp. 247-252.
  8. J.-G. Kim, H.-M. Kwon, D.-H. Kim, and T.-W. Kim, "Impact of in situ atomic layer deposition TiN/high- κ stack onto In 0.53 Ga 0.47 As MOSCAPs on 300 mm Si substrate", Jpn. J. Appl. Phys., Vol. 58, No. 4, pp. 040905(1)-040905(4), 2019.
  9. R. Engel-Herbert, Y. Hwang, and S. Stemmer, "Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces," J. Appl. Phys., Vol. 108, No. 12, pp. 124101(1)-124101(15), 2010. https://doi.org/10.1063/1.3520431