• 제목/요약/키워드: Threshold-Voltage

검색결과 1,291건 처리시간 0.032초

As-Ge-Te 메모리 스위칭 소자의 전도 및 스위칭 전압 특성 (The Characteristics of Conduction rind Switching Voltage for As-Ge-Te Memory Switching Device)

  • 이병석;이현용;이영종;정흥배
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1995년도 추계학술대회 논문집
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    • pp.67-70
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    • 1995
  • Amorpous As$\sub$10/Ge$\sub$15/Te$\sub$75/ device shows the memory switching characterisite under d.c. bias. In bulk material, a-As$\sub$10/Ge/sub15/Te$\sub$75/s switching voltage range is above 100 volts. Our purposes in this gaudy are decreasing a switching threshold voltage, finding the properties of d.c., a.c. conduction, and the characterisitics of switching threshold voltage fur a-As$\sub$10/Ge$\sub$15/Te$\sub$75/. As the results, the d.c.and a.c. conductivities increase with temperature. From the data of conductivity, various electrical and physical properties are obtained experimentally. The switching threshold voltages decrease with increasing annealing temperature and time, but increase with increasing film thickness and distance of electrode for d.c. bias.

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Substrate 물질에 따른 a-IGZO TFT의 온도 특성 (Characteristics of a-IGZO TFT by the material of substrate and temperature)

  • 이명언;정한욱;박현호;최병덕
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2010년도 하계학술대회 논문집
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    • pp.148-148
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    • 2010
  • Measuring the a-IGZO TFTs with various temperatures was found to induce a threshold voltage shift and a change of the subthreshold gate voltage swing. Characteristic change is dependant on a material of the substrate at the temperature from $20^{\circ}C$ to $100^{\circ}C$. The threshold voltage was shifted to the left from -2.7V to -61V on SiO2/galss. But, as the temperature increases form $20^{\circ}C$ to $100^{\circ}C$. the threshold voltage was shifted to the right from 0.85V to 2.45V.

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잉크젯 프린팅으로 제작된 유기 박막 트랜지스터의 이력특성 분석 (Hysteresis characteristics of organic thin film transistors using inkjet printing)

  • 구남희;송승현;최길복;송근규;김보성;신성식;정윤하
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.557-558
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    • 2006
  • In this paper, the hysteresis characteristics by bias stress in organic thin film transistors using inkjet printing were investigated. Electron trapping increased threshold voltage for positive gate bias stress and hole trapping decreased threshold voltage for negative gate bias stress. From these phenomena, highly reproducible measurement method which minimized threshold voltage shift by choosing the proper range of gate voltage was suggested. Using this measurement method, we found that electron trapping as well as hole trapping had important influence on hysteresis characteristics.

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Hot electron에 의하여 노쇠화된 PMOSFET의 문턱전압과 유효 채널길이 모델링 (The Threshold Voltage and the Effective Channel Length Modeling of Degraded PMOSFET due to Hot Electron)

  • 홍성택;박종태
    • 전자공학회논문지A
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    • 제31A권8호
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    • pp.72-79
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    • 1994
  • In this paper semi empirical models are presented for the hot electron induced threshold voltage shift(${\Delta}V_{t}$) and effective channel shortening length (${\Delta}L_{H}$) in degraded PMOSFET. Trapped electron charges in gate oxide are calculated from the well known gate current model and ΔLS1HT is calculated by using trapped electron charges. (${\Delta}L_{H}$) is a function of gate stress voltage such as threshold voltage shift and degradation of drain current. From the correlation between (${\Delta}L_{H}$) has a logarithmic function of stress time. From the measured results, (${\Delta}V_{t}$) and (${\Delta}L_{H}$) are function of initial gate current and device channel length.

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Twin-well 구조로 제작된 N채널 및 P채널 FET의 특성 (Characteristics of N-and P-Channel FETs Fabricated with Twin-Well Structure)

  • 김동석;이철인;서용진;김태형;김창일;장의구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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    • pp.86-90
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    • 1992
  • We have studied the characteristics of n-and p-channel FETs with submicron channel length fabricated by twin-well process. Threshold voltage variation and potential distribution with channel ion implantation conditions and impurity profile of n-and p-channel region wee simulated using SUPREM-II and MINIMOS 4.0 simulater, P-channel FET had buried-channel in the depth of 0.15 $\mu\textrm{m}$ from surface by counter-doped boron ion implantation for threshold voltage adjustment. As a result of device measurement, we have obtained good drain saturation characteristics for 3.3 [V] opreation, minimized short channel effect with threshold voltage shift below 0.2[V], high punchthrough and breakdown voltage above 10[V] and low subthreshold value.

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스트레스 인가에 의한 다결정 실리콘 박막 트랜지스터의 열화 특성 (Degradation of Polycrystalline Silicon Thin Film Transistor by Inducing Stress)

  • 백도현;이용재
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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    • pp.322-325
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    • 2000
  • N-channel poly-Si TFT, Processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after electrical stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5$\mu\textrm{m}$ and 3$\mu\textrm{m}$ poly-Si TFTs are 3.3V, 3.V respectively. With the threshold voltage shia the degradation of transconductance(G$\_$m/) and subthreshold swing(S) is also observed.

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Stress-Bias Effect on Poly-Si TFT's on Glass Substrate

  • Baek, Do-Hyun;Yong Jae lee
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 ITC-CSCC -2
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    • pp.933-936
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    • 2000
  • N-channel poly-Si TFT, processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5um and 3um poly-Si TFT’s are 3.3V, 37V respectively. With the threshold voltage shift, the degradation of transconductance and subthreshold swing is also observed.

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Analysis and Remedy of TFT Based Current Mode Logic Circuit Performance Degradation due to Device Parameter Fluctuation

  • Lee, Joon-Chang;Jeong, Ju-Young
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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    • pp.535-538
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    • 2005
  • We report the influence of the threshold voltage and mobility fluctuation in TFT on current mode digital circuit performance. We found that the threshold voltage showed more serious circuit malfunction. We studied new circuit configuration for improvement.

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두 개의 P-플로팅 층을 가지는 새로운 IGBT에 관한 연구 (A Novel IGBT with Double P-floating layers)

  • 이재인;최종찬;양성민;성만영
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.14-15
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    • 2009
  • Insulated Gate Bipolar Transistor(IGBTs) are widely used in power device industry. However, to improve the breakdown voltage, IGBTs are suffered from increasing on-state voltage drop due to structural design. In this paper, the new structure is proposed to solve this problem. The proposed structure has double p-floating layer inserted in n-drift layer. The p-floating layers improve the breakdown voltage compared to conventional IGBT without change of other electrical characteristics such as on-state voltage drop and threshold voltage. this is because the p-floating layers expand electric field distribution at blocking state. A electrical characteristic of proposed structure is analyzed by using simulators such as TSUPREM and MEDICI. As a result, on-state voltage drop and threshold voltage are same to a conventional TIGBT, but breakdown voltage is improved to 16%.

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