• 마이크로전자및패키징학회지
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• 제24권4호
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• 조명전기설비학회논문지
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• 제24권12호
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• pp.57-63
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• 2010

The efficiency of LED package is increasing by applying the high power, and a existing lighting is changing as the LED lighting. However, many problems have appeared by heat. Therefore, in order to solve thermal problems, LED lighting is designing in several ways, but the advantages of LED lighting is fading due to increase the prices and volumes. In this study, we try to improve the thermal performance by formation of via holes. The junction temperature and thermal resistance in the FR4-PCB with via-holes of 0.6[mm] was excellent in experiment and FR4-PCB with Via-holes of 0.6[mm] was excellent in simulation without solder. Further, the thermal resistance and the optical properties can be improved through a formation of via-holes.

• 마이크로전자및패키징학회지
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• 제10권1호
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• pp.39-43
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• 2003

열전달에 대해 고려하는 것은 LTCC와 같은 고밀도 회로기판을 설계하는데 매우 중요한 요소이다. 본 연구에서는 열전달 효과를 조사하기 위해서 LTCC 기판 내에 열 비아 및 패드를 위치시킨 기판을 제작하였다. 제작된 기판의 정확한 열적인 분석을 이해하기 위해서 Laser Flash Method에 의한 샘플의 열전도도 분석 및 수치해석을 수행하였다. 열비아 및 열방출을 위한 패드로 구성된 LTCC 기판의 열전도 특성은 순수 Ag재료의 44%인 103 W/mK 값을 초과하는 특성을 나타내었다. 수치해석에 의해서 LTCC 기판내의 비아 배열, 크기, 밀도 변화에 따른 열거동의 해석을 수행하였다.

• 한국전기전자재료학회논문지
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• 제24권3호
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• pp.234-239
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• 2011

In this study, the heat transfer capability have been improved by using via-holes in FR4 PCB, when the LED lighting is designed to solve the thermal problem. The thermal resistance and junction temperature were measured by changing the dimension of FR4 PCB and size of via hole. As a result, when the dimension was increased initially, the thermal resistance and junction temperature was decreased rapidly, the ones was stabilized after the dimension of 200 $[mm^2]$. Also, the light output was improved up to maximum 17% by formation of via-hole and expansion of dimension in FR4 PCB. Therefore, the thermal resistance and junction temperature could be improved by expansion of PCB dimension and configuration of via-hole ability.

• 전기학회논문지
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• 제59권11호
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• pp.2038-2042
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• 2010

In this paper, we confirmed the thermal & optical properties for improving the heat transfer coefficient by changing the via hole size and in FR4 PCB with the same area. Osram 1W power LED Package (Golden Dragon) was used and the K-factor which is relative constant between LED junction temperature and forward bias was measured with power source meter(KEITHLEY 2430) to measure the thermal resistance from PCB configuration. As results, thermal resistance in metal PCB came out to the lowest as $26 [^{\circ}C/W]$ and thermal resistance in FR4 PCB without via-holes emerged as the highest as $69 [^{\circ}C/W]$. However thermal resistance of FR4 PCB could have decreased until $32[^{\circ}C/W]$ in 0.6 mm by using the via hole. Also, the luminous flux could have improved, too.

• Journal of Welding and Joining
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• 제29권1호
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• pp.46-51
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• 2011

TSV technology raises several reliability concerns particularly caused by thermally induced stress. In traditional package, the thermo-mechanical failure mostly occurs as a result of the damage in the solder joint. In TSV technology, however, the driving failure may be TSV interconnects. In this study, the thermomechanical reliability of TSV technology is investigated using finite element method. Thermal stress and thermal fatigue phenomenon caused by repetitive temperature cycling are analyzed, and possible failure locations are discussed. In particular, the effects of via size, via pitch and bonding pad on thermo-mechanical reliability are investigated. The plastic strain generally increases with via size increases. Therefore, expected thermal fatigue life also increase as the via size decreases. However, the small via shows the higher von Mises stress. This means that smaller vias are not always safe despite their longer life expectancy. Therefore careful design consideration of via size and pitch is required for reliability improvement. Also the bonding pad design is important for enhancing the reliability of TSV structure.

• 한국산학기술학회논문지
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• 제13권10호
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• pp.4757-4761
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• 2012

알루미늄 기판 및 양극산화 공정을 사용하여 LED Chip on Board(COB) 패키지를 제작하였다. 선택적 양극산화 공정을 적용하여 알루미늄 기판 상에 알루미나를 형성하고 이를 COB 패키지 절연층으로 사용하였으며, 비아홀 내부가 충진된 구조의 Thermal Via를 구현하였다. 패키지 기판 종류에 따른 열저항 및 발광효율 변화를 파악하기 위해 알루미늄 기판과 알루미나 기판을 제작하고 이를 각각 비교 분석하였다. Thermal Via가 적용된 알루미늄 기판이 51%의 열저항 개선 및 14%의 발광효율 향상 특성을 보여주었다. 이러한 결과는 선택적 양극산화 공정 및 Thermal Via 구조적용으로 COB 패키지의 방열 특성이 향상되었음을 의미한다. 또한 동일한 전력 소모시 LED 칩 개수에 따른 COB 패키지의 열저항 및 발광효율 변화를 분석함으로써 다수 칩의 효율적인 배치가 열저항 및 발광효율을 증가시킬 수 있음을 확인하였다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.153-157
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• 2002

Thermal management is very important for the success of high density circuit design in LTCC. To realized more accurate thermal analysis for structure design, a series of simple thermal resistance measurement by laser flash method and parametric numerical analysis have been carried out. The design of via filled material would be useful in thermal management of power devices.

• 마이크로전자및패키징학회지
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• 제24권1호
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• 한국전기전자재료학회논문지
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• 제36권1호
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• pp.23-28
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• 2023

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.