• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.12
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• pp.57-63
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• 2010

The efficiency of LED package is increasing by applying the high power, and a existing lighting is changing as the LED lighting. However, many problems have appeared by heat. Therefore, in order to solve thermal problems, LED lighting is designing in several ways, but the advantages of LED lighting is fading due to increase the prices and volumes. In this study, we try to improve the thermal performance by formation of via holes. The junction temperature and thermal resistance in the FR4-PCB with via-holes of 0.6[mm] was excellent in experiment and FR4-PCB with Via-holes of 0.6[mm] was excellent in simulation without solder. Further, the thermal resistance and the optical properties can be improved through a formation of via-holes.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.1
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• pp.39-43
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• 2003

Thermal management is very important for the success of high density circuit design in LTCC. In this paper, LTCC substrates containing thermal via and pad were fabricated in order to study the influence of the thermal dissipation. To realize the accurate thermal analysis for structure design, a series of simple thermal conductivity measurement by laser flash method and parametric numerical analysis have been carried out. The LTCC substrate including via and Ag pad has good thermal conductivity over 103 W/mK which is 44% value of pure Ag material. Thermal behaviors with via arrays, size and density in the LTCC substrate were studied by numerical method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.3
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• pp.234-239
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• 2011

In this study, the heat transfer capability have been improved by using via-holes in FR4 PCB, when the LED lighting is designed to solve the thermal problem. The thermal resistance and junction temperature were measured by changing the dimension of FR4 PCB and size of via hole. As a result, when the dimension was increased initially, the thermal resistance and junction temperature was decreased rapidly, the ones was stabilized after the dimension of 200 $[mm^2]$. Also, the light output was improved up to maximum 17% by formation of via-hole and expansion of dimension in FR4 PCB. Therefore, the thermal resistance and junction temperature could be improved by expansion of PCB dimension and configuration of via-hole ability.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.11
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• pp.2038-2042
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• 2010

In this paper, we confirmed the thermal & optical properties for improving the heat transfer coefficient by changing the via hole size and in FR4 PCB with the same area. Osram 1W power LED Package (Golden Dragon) was used and the K-factor which is relative constant between LED junction temperature and forward bias was measured with power source meter(KEITHLEY 2430) to measure the thermal resistance from PCB configuration. As results, thermal resistance in metal PCB came out to the lowest as $26 [^{\circ}C/W]$ and thermal resistance in FR4 PCB without via-holes emerged as the highest as $69 [^{\circ}C/W]$. However thermal resistance of FR4 PCB could have decreased until $32[^{\circ}C/W]$ in 0.6 mm by using the via hole. Also, the luminous flux could have improved, too.

• Journal of Welding and Joining
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• v.29 no.1
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• pp.46-51
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• 2011

TSV technology raises several reliability concerns particularly caused by thermally induced stress. In traditional package, the thermo-mechanical failure mostly occurs as a result of the damage in the solder joint. In TSV technology, however, the driving failure may be TSV interconnects. In this study, the thermomechanical reliability of TSV technology is investigated using finite element method. Thermal stress and thermal fatigue phenomenon caused by repetitive temperature cycling are analyzed, and possible failure locations are discussed. In particular, the effects of via size, via pitch and bonding pad on thermo-mechanical reliability are investigated. The plastic strain generally increases with via size increases. Therefore, expected thermal fatigue life also increase as the via size decreases. However, the small via shows the higher von Mises stress. This means that smaller vias are not always safe despite their longer life expectancy. Therefore careful design consideration of via size and pitch is required for reliability improvement. Also the bonding pad design is important for enhancing the reliability of TSV structure.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.10
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• pp.4757-4761
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• 2012

LED chip on board(COB) package has been fabricated using aluminum substrate and aluminum anodization process. An alumina layer, used as a dielectric in COB substrate, is produced on aluminum substrate by selective anodization process. Also, selective anodization process makes it possible to construct a thermal via with a fully-filled via hole. Two types of the COB package are fabricated in order to analyze the effects of their substrate types on thermal resistivity and luminous efficiency. The aluminum substrate with the thermal via shows more improved measurement results compared with the alumina substrate. These results demonstrate that selective anodization process and thermal via can increase heat dissipation of COB package in this work. In addition, it is proved experimentally that these parameters also can be enhanced using efficient layout of multiple chip in the COB package.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.153-157
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• 2002

Thermal management is very important for the success of high density circuit design in LTCC. To realized more accurate thermal analysis for structure design, a series of simple thermal resistance measurement by laser flash method and parametric numerical analysis have been carried out. The design of via filled material would be useful in thermal management of power devices.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.23-28
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• 2023

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.