• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.128-133
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• 1994

This paper proposes a new TTL-to-CMOS converter which has low power dissipation. This converter has no static power dissipation for typical TTL output voltage levels. The simulatio result shows that the power dissipation is reduced to about 1/20 of conventional level converter using CMOS inverters. It also has hysteresis due to the positive feedback which makes the converter noise immune. The logic threshold voltages in the hysteresis characteristic can be optimized by changing the size ratios of the transistors.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.52-58
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• 2001

This paper describes a TTL-to-CMOS input buffer of an SRAM which dissipates a small operating power dissipation. The input buffer utilizes a transistor structure with latch circuit controlled by a internal activation clock pulse. During the low state of that pulse, input buffer is disabled to eliminate dc current. Otherwise, the input buffer operates normally. Simulation results showed that the power-delay product of the purposed input buffer is reduced by 33.7% per one input.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1512-1513
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• 2007

In this paper the influence of CMOS- and TTL-technology on the breakdown and destruction effects by artificial electromagnetic waves is determined. Different electronic devices(3 CMOS & 5 TTL) were exposed to high amplitude electromagnetic waves. CMOS ICs were occurred only destruction below the max electric field and TTL ICs were occurred breakdown and destruction below the max electric field. The SEM analysis of the destruction devices showed onchipwire and bondwire destruction like melting due to thermal effect. The test results are applied to the data which understand electromagnetic wave effects of electronic equipments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1A
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• pp.47-53
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• 2003

This paper describes the design of a 155 Mb/s multiplexer-demultiplexer chip. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s serial data output, and is to deinterleave a serial input bit stream of 155 Mb/s into the parallel output of 51 Mb/s The input and output of the device are TTL compatible at the low-speed end, but 100K ECL compatible at the high-speed end The device has been fabricated with a 0.7${\mu}m$ BiCMOS gate array The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 470 ps at the high-speed end. And power dissipation is evaluated under 2.0W.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.56-63
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• 2011

This paper presents the method of giving hysteresis characteristics to the digital input port of microprocessors or micro-controllers and it's design procedures. And this paper shows the example of circuit design and the effect of this method by experiments. Presented method has advantages : By the additional one port and two resistors, input port can have hysteresis characteristics and hysteresis band is larger than TTL, CMOS schmitt trigger gates.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.345-348
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• 2000

In this paper, We described the procedures to generate an input-output buffer information specification (IBIS) model in digital IC circuits. We gives the method to describe IBIS standard I/O for the characteristics of I/O buffer and to represent its electrical characteristics. The parameters of I/O structure for I/O buffer modelling are also referred, and an IBIS model for CMOS, TTL IC, ROM and RAM constructed amounts about 216. This IBIS model can be used to the simulation of signal integrity of high speed circuits in a PCB level.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.16-25
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• 1997

This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.

• IT SoC Magazine
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• s.3
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• pp.35-37
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• 2004

본 연구팀이 Hynix 0.35um CMOS 4M 2P 공정을 사용하여 제작한 민수용 DDFS (DAC를 포함한 single chip)는 DC부터 100MHz 까지 사용할 수 있으며(BW=100MHz) frequency 변환속도 약 30nS, 주파수해상도 0.0745Hz, 그리고 소비 전력은 120MHz 클럭에서 약 200mW이다. 본고에서는 언급하지 않았지만, 본 연구팀이 별도의 설계로 진행된 군수용 DDFS의 경우, 출력주파수는 DC부터 320MHz 까지 가능하고 소비 전력은 800MHz 클럭에서 약 400mW이다. 이처럼 DDFS는 특성 자체의 우수성 뿐 아니라, 각종 멀티미디어 기기 및 통신시스템의 급격한 디지털화 추세로 인해 주파수합성기도 디지털화 함으로써 VLSI화가 용이하고, 이에 따라 S/W에 의한 다기능화 (programmability), 응용성의 극대화, 및 저가격화를 추구할 수 있다는 점에서 주목해야 할 분야이다. 특히 반도체기술의 발전으로 지금까지 DDFS 구현의 가장 큰 장애로 대두되던 DAC의 고속화가 부분적으로 가능해지면서 (TTL-to-ECL interface 부가회로가 별도로 필요없이 직접적인 연결), DDFS의 시장 전망을 더욱 밝게 하고 있다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.61-70
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• 1996

In this paper, we find the values of near-end crosstalk coefficient in striplines of a FR-4 multilayer PCB by an analytic method and a HSPICE simulation method, and define calcualtion errors in an analytic method and define the application range, and simualte near-end crosstalk coefficients of the FCT (fast CMOS TTL) in complicated striplines by HSPICE and analyze near-en crosstalk coefficients in relation to dielectric thickness and trace spaces of striplines. As a result, we analyze coupling structure of the near-end crosstalk in the coplicated sstriplines that are impedance matched and define a coupling formula of near-end crosstalk coefficients in general complicated striplines. Especially, it is approximated in the layout grade rule.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.4
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.