• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.332-336
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• 2001

In this study, the reaction at UBM(Under Bump Metallurgy) and solder interface was investigated. The UBM employed in conventional optical packages, Au/Pt/Ti layer, were found to dissolve into molten Au-Sn eutectic solder during reflow soldering. Therefore, the reaction with different diffusion barrier layer such as Fe, Co, Ni were investigated to replace the conventional R layer. The reaction behavior was investigated by reflowing the solder on the pad of the metals defined by Cr layer for 1, 2, 3, 4, and 5 minutes at 330$^{\circ}C$. Among the metals, Co was found to be most suitable for the diffusion barrier layer as the wettability with the solder was reasonable and the reaction rate of intermetallic formation at the interface is relatively slow.

• Journal of Welding and Joining
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• v.26 no.1
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• pp.24-30
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• 2008

• Proceedings of the Materials Research Society of Korea Conference
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• 2000.11a
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• pp.147-147
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• 2000

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Journal of the Korean Society for Precision Engineering
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• v.26 no.12
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• pp.18-22
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• 2009

• Proceedings of the KWS Conference
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• 2002.10a
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• pp.439-449
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• 2002

This paper reviews our recent research works on the interconnection technologies in electronic packaging and assembly. At the aspect of advanced joining methods, laser-ultrasonic fluxless soldering technology was proposed. The characteristic of this technology is that the oxide film was removed through the vibration excitated by high frequency laser change in the molten solder droplet. Application researches of laser soldering technology on solder bumping of BGA packages were carried out. Furthermore, interfacial reaction between SnPb eutectic solder and Au/Ni/Cu pad during laser reflow was analyzed. At the aspect of soldered joints' reliability, the system for predicting and analyzing SMT solder joint shape and reliability(PSAR) has been designed. Optimization design method of soldered joints' structure was brought forward after the investigation of fatigue failure of RC chip devices and BGA packages under temperature cyclic conditions with FEM analysis and experimental study. At the aspect of solder alloy design, alloy design method based on quantum was proposed. The macroproperties such as melting point, wettability and strength were described by the electron parameters. In this way, a great deal of the experimental investigations was replaced, so as to realize the design and research of any kinds of solder alloys with low cost and high efficiency.

• ETRI Journal
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• v.35 no.4
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

• Journal of the Korean institute of surface engineering
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• v.50 no.3
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• pp.155-163
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• 2017

In this study, the effects of the concentration of metal ions and the applied current density in the Sn-Ag plating solutions were examined in regards to the resulting composition and morphology of the solder bumps' surface. Furthermore the effect of any impurities present in the methanesulfonic acid used as a base acid in the Sn-Ag solder plating solution on the stability of plating solution as well as the characteristics of the Sn-Ag alloys films was also explored. As expected, the uniform bump was obtained by means of removing impurities in the plating solution. Consequently the resultant solder bump was obtained in an optimal current density of the range of $1A/dm^2$ to $15A/dm^2$, which has acceptable bump shape and surface roughness with 12inch wafer trial results.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.169-173
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• 2003

We demonstrated the applicability of dry film photoresist (DFR) in photolithography process for fine pitch solder bumping on the polytetrafluoroethylene (PTFE/Teflon) printed circuit board (PCB). The copper lines were formed with $100\;{\mu}m$ width and $18\;{\mu}m$ thickness on the PTFE test board, and varying the gaps between two copper lines in a range of $100-200\;{\mu}m$. The DFRs of $15\;{\mu}m$ thickness were laminated by hot roll laminator, by varying laminating temperature from $100^{\circ}C\;to\;150^{\circ}C$ and laminating speed. We found the optimum process of DFR lamination on PTFE PCB and accomplished the formation of indium solder bumps. The optimum lamination condition was temperature of $150^{\circ}C$ and speed of about 0.63 cm/s. And the smallest size of indium solder bump was diameter of $50\;{\mu}m$ with pitch of $100\;{\mu}m$.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.193-205
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• 2001