Technologies of TSV Filling and Solder Bumping for 3D Packaging

TSV 충진 및 3D 패키징 솔더 범핑 기술

  • 유세훈 (한국생산기술연구원 마이크로조이닝센터) ;
  • 고영기 (한국생산기술연구원 마이크로조이닝센터) ;
  • 신의선 (한국생산기술연구원 마이크로조이닝센터) ;
  • 이창우 (한국생산기술연구원 마이크로조이닝센터)
  • Published : 2009.12.01

Abstract

Keywords

References

  1. Jiang, T. and Luo, S., "3D Integration-Present and Future," Proceedings of 10th Electronics Packaging Technology Conferences, pp. 373-378, 2008
  2. Curran, B., Ndip, I., Guttovski, S. and Reichl, H., "Managing Losses in Through Silicon vias with Different Return Current Path Configurations," Proceedings of 10th Electronics Packaging Technology Conferences, pp. 206-211, 2008
  3. Dixit, P, Chen, X., Miao, J., Divakaran, S. and Preisser, R., "Study of surface treatment processes for improvement in the wettability of silicon-based materials used in high aspect ratio through-via copper electroplating," Applied Surface Sicence, Vol. 253, No. 21, pp. 8637-8646, 2007 https://doi.org/10.1016/j.apsusc.2007.04.067
  4. Sun, J., Kondo, K., Okamura, T., Oh, S., Tomisaka, M., Yonemura, H., Hoshino, M. and Takahashi, K., "High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking," Journal of the Electrochemical Society, Vol. 150, No.6, pp. 0355-0358, 2003 https://doi.org/10.1149/1.1572154
  5. Chang, G. and Lee, J., "The Effect of Current Types on Through Via Hole Filling for 3D-SiP Application," Journal of the Microelectronics & Packaging Society, Vol. 13, No.4, pp. 45-50, 2006
  6. Lee, S. and Lee, J., "Copper Via Filling Using Organic Additives and Wave Current Electroplating," Journal of Microelectronics & Packaging Society, Vol. 14, No.3, pp. 37-42, 2007
  7. Song, C., Wang, Z., Chen, Q., Cai, J. and Liu, L., "High aspect ratio copper through-silicon-vias for 3D integration," Microelectronic Engineering, Vol. 85, No. 10, pp. 1952-1956, 2008 https://doi.org/10.1016/j.mee.2008.05.017
  8. Park, S., Oh, T., Eum, Y. and Moon, J., "Interconnection Processes Using Cu Vias for MEMS Sensor Packages," Journal of the Microelectronics & Packaging Society, Vol. 14, No.4, pp. 63-69, 2007
  9. Chang, D., Ryu, C., Lee, K., Cho, B., Kim, J., Oh, T., Lee, W. and Yu, Y., "Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias(TSV)," Proceedings of the Electronics Components Technology conference, pp. 847-852, 2007
  10. Lee, Y., Yu, J., Park, K. and Oh, T., "Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package," Journal of Electronic Materials, Vol. 38, No.5, pp. 685-690, 2009 https://doi.org/10.1007/s11664-008-0646-6
  11. Chen, N., Fan, A., Tan, C. and Reif, R., "Bonding Parameters of Blanket Copper Wafer Bonding," Journal of Electronic Materials, Vol. 35, No.2, pp. 230-234, 2006 https://doi.org/10.1007/BF02692440
  12. Ang, X., Lin, A., Wei, J., Chen, Z. and Wong, C., "Low Temperature Copper-Copper Thermocompression Bonding," Proceedings of the Electronics Components Technology Conference, pp. 399-404, 2007
  13. Chen, K., Tan, C., Fan, A. and Reif, R., "Morphology and Bond Strength of Copper Wafer Bonding," Electrochemical Solid-State Letters, Vol. 7, No. 1, pp. G14-G16, 2004 https://doi.org/10.1149/1.1626994
  14. Tan, C., Chen, K., Fan, A. and Reif, R., "The Effect of Forming Gas Anneal on the Oxygen Content in Bonded Copper Layer," Journal of Electronic Materials, Vol. 34, No. 12, pp. 1598-1602, 2005 https://doi.org/10.1007/s11664-005-0171-9