• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.163-166
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2\;and\;Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability

• Proceedings of the Optical Society of Korea Conference
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• 2003.02a
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• pp.172-173
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• 2003

SOI (Silicon on insulator) 웨이퍼를 이용하여 제작된 전자소자는 고온에서 동작이 안정될 뿐만 아니라 초고속 동작이 가능하고, 사용 소비전력이 낮고, 단위 소자의 집적 효율이 우수해 활발한 연구가 이루어지고 있다. 최근에 초고속 광소자와 단위 광소자들의 집적을 위해 Si 이외의 GaAs, InP, SIC 등의 반도체 박막을 절연층 위에 만드는 연구가 많이 진행되고 있다 따라서 초기에 절연체 위에 실리콘 박막을 형성하는 Silicon on insulator (SOI) 기술은 다양한 종류의 반도체 박막을 절연체 위에 형성하는 Semiconductor on insulator로 SOI의 의미가 확장되고 있다. (중략)

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.147-152
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• 2016

In this study, we fabricated Ag-based electrochemical metallization memory devices which is also called conductive-bridge random-access memory (CBRAM) in order to investigate the resistive switching behavior depending on the bottom electrode (BE). RRAM cells of two different layer configurations having $Ag/Si_3N_4/TiN$ and $Ag/Si_3N_4/p^+$ Si are studied for metal-insulator-metal (MIM) and metal-insulator-silicon (MIS) structures, respectively. Switching voltages including forming/set/reset are lower for MIM than for MIS structure. It is found that the workfunction different affects the performances.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.83-83
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• 2008

Metal-oxide-silicon-on-insulator (MOSOI) structures were fabricated to study the effect caused by reactive ion etching (RIE) and sacrificial oxidation process on silicon-on-insulator (SOI) layer. The MOSOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching treatment. The measured C-V curves were compared to the numerical results from 2-dimensional (2-D) simulations. The measurements revealed that the profile of C-V curves significantly changes depending on the SOI surface condition of the MOSOI capacitors. The shift in the measured C-V curves, due to the difference of the fixed oxide charge ($Q_f$), together with the numerical simulation analysis and atomic force microscopy (AFM) analysis, allowed extracting the fixed oxide charges ($Q_f$) in the structures as well as 2-D carrier distribution profiles.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.100-105
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• 1994

Analytical expressions for the breakdown voltage and the optimum drift region length (L$_{dr}$) of SOI (Silicon-On-Insulator) pn diodes are derived in terms of the doping concentration and the thickness of the n- drift region and the buried oxide thickness. The optimum L$_{dr}$ is obtained from the condition that the breakdown voltage of the vertical electric field of n+n- junction equals to the of the lateral electric field of n+n-p+ junction. Analytical results agree reasonably with the numerical simulations using PISCESII.

• KIEE International Transactions on Electrophysics and Applications
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• v.2C no.5
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• pp.258-261
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• 2002

Electrical forming dependent current-voltage (I-V) and numerically derived differential conductance(dI／dV) characteristics have been presented in the multi-layer nano-crystalline silicon／oxygen (no-Si／O) superlattice. Distinct staircase-like features, indicating the presence of resonant tunnel barriers, are clearly observed in the dc I-V characteristics. Also, all samples showed a continuous change in current and zero conductivity around OV corresponding to the Coulomb blockade in the calculated dI／dV-V curve. Also, Ra-man scattering measurement showed the presence of a nano-crystalline Si structure. This result becomes a step in the right direction for the fabrication of silicon-based optoelectronic and quantum devices as well as for the replacement of silicon-on-insulator (SOI) in high speed and low power silicon MOSFET devices of the future.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.4
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• pp.161-168
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• 2001

Organic thin film transitors(TFTs) are of interest for use in broad area electronic applications. For example, in active matrix liquid crystal displays(AMLCDs), organic TFTs would allow the use of inexpensive, light-weight, flexible, and mechanically rugged plastic substrates as an alternative to the glass substrates needed for commonly used hydrogenated amorphous silicon(a-Si:H). Recently pentacene TFTs with carrier field effect, mobility as large as 2 $cm^2V^{-1}s^{-1}$ have been reported for TFTs fabricated on silicon substrates, and it is higher than that of a-Si:H. But these TFTs are fabricated on silicon wafer and $SiO_2$ was used as a gate insulator. $SiO_2$ deposition process requires a high insulator which is polyimide and photo acryl. We investigated trasfer and output characteristics of the thin film transistors having active layer of pentacene. We calculated field effect mobility and on/off ratio from transfer characteristics of pentacene thin film transistor, and measured IR absorption spectrum of polymide used as the gate dielectric layer. It was found that using the photo acryl as a gate insulator, threshold voltage decreased from -12.5 V to -7 V, field effect mobility increased from 0.012 $cm^2V^{-1}s^{-1}$ to 0.039 $cm^2V^{-1}s^{-1}$ , and on/off current ratio increased from $10^5\;to\;10^6$. It seems that TFTs using photo acryl gate insulator is apt to form channel than TFTs using polyimide gate insulator.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.199-199
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• 2010

A back-gated MOSFET on silicon-on-insulator (SOI) substrate for pH sensor was investigated. We used concentrations of pH solution from 6 to 9. The fabricated back-gated MOSFET has current difference and threshold voltage shift by pH concentrations. Therefore, It can be used to simplification of conventional pH sensor.