• Journal of information and communication convergence engineering
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• 제4권2호
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• pp.88-91
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• 2006

In this paper, a novel physical structure for planar spiral inductors is proposed. The spiral inductors were designed and fabricated on multi-layered substrate Bragg-reflector/silicon (BR/Si) wafer. The impacts of multi-layered structure substrate and pattern on characteristics of inductor were studied. Experimental results show that the inductor embedded on Bragg reflector/silicon substrate can achieve the best improvement. At 0.4-1.6 GHz, the Bragg reflector seems to significantly increase the S11-parameter of the inductor.

• 한국결정성장학회지
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• 제18권1호
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• pp.38-44
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• 2008

c-축 배향을 갖는 MFI 제올라이트 필름$(<35{\mu}m)$을 종자결정 성장법을 이용하여 실리카라이트-1 종자결정이 도포된 알루미나와 실리콘 지지체 위에 성장시켰다. 지지체 표변에서 성장된 필름은 전자현미경과 X- 회절 분석을 이용하여 조사하였다. 지지체 표면의 거친 정도에 따른 필름의 성장에 미치는 영향에 대해서 조사하였으며 c- 축 배향을 갖는 필름과 종자결정 성장법에서 나타나는 특징적인 돔 형태의 결함구조의 생성과 반응기구에 대해서 설명하였다. 지지체 표면의 거친 정도가 c- 축 배향에 중요한 역할을 하였다.

• 한국표면공학회지
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• 제29권5호
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• pp.577-584
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• 1996

Silicon oxide films with high hardness and water repellency were prepared by microwave plasma-enhanced CVD using four kind of organosilicon compound-fluoro-alkyl silane mixtures as source gases. An argon gas was used as a carrier gas for fluoro-alkyl silane. The substrate temperatures during deposition were controlled by resistant heating at a constant value between 50 and $300^{\circ}C$. The hardness of the films increased, but the deposition rate and the contact angle for a water drop decreased with increasing substrate temperature. The number of methoxy groups also affected the water repellency and hardness. The deposited films became more inorganic with increasing substrate temperature because of the thermal dissociation of reactants.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2006년도 춘계종합학술대회
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• pp.255-258
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• 2006

In this paper, a novel physical structure for planar spiral inductors is proposed. The spiral inductors were designed and fabricated on multi-layered substrate Bragg-reflector/silicon (BR/Si) wafer. The impacts of multi-layered structure substrate and pattern on characteristics of inductor were studied. Experimental results show that the inductor embedded on Bragg reflector/silicon substrate can achieve the best improvement. At 0.4-1.6 GHz, the Bragg reflector seems to significantly increase the $S_{11}-parameter$ of the inductor.

• 마이크로전자및패키징학회지
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• 제20권3호
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• pp.23-29
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• 2013

현재까지 유연한 전자소자 개발은 주로 인쇄전자 기술을 이용한 유기재료 기반 위주로 연구 및 개발이 진행되어 오고 있다. 그러나 유기 기반의 소자는 성능 및 신뢰성에 많은 제약이 있다. 따라서 본 논문에서는 무기재료 기반의 실리콘 고성능 유연 전자소자를 개발하기 위한 방법으로 나노 및 마이크로 두께의 단결정 실리콘 박막을 transfer printing 기술을 이용하여 유연기판에 전사하여 제작하였다. 제작된 유연소자는 굽힘 시험과 인장 시험을 통하여 유연 신뢰성을 평가하였다. PI 기판에 부착된 두께 200 nm의 박막은 굽힘 시험 결과, 곡률 반경 4.8 mm 까지 굽힐 수 있었으며, 따라서 굽힘 유연성이 매우 우수함을 알 수 있었다. 인장 시험 결과 인장 변형률 1.8%에서 박막이 파괴되었으며, 기존 실리콘 박막에 비하여 연신율이 최대 1% 증가됨을 알 수 있었다. FPCB 기판에 부착된 마이크로 두께의 실리콘 박막의 경우 칩이 얇아질수록 굽힘 유연성이 향상됨을 알 수 있었으며, $20{\mu}m$ 두께의 박막의 경우 곡률 반경 2.5 mm 까지 굽힐 수 있음을 알 수 있었다. 이러한 유연성의 증가는 실리콘 박막과 유연 기판 사이의 접착제의 완충작용 때문이다. 따라서 유연 전자소자의 유연성을 증가시키기 위해서는 박막 제작 시 공정 중의 결함을 최소화하고, 적절한 접착제를 사용한다면 유연성을 크게 증가시킬 수 있음을 알 수 있었다.

• 한국결정성장학회지
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• 제18권4호
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• pp.137-139
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• 2008

Floating zone, neutron transmutation-doped and magnetic Czochralski silicon crystals are being widely used for fabrication power devices. To improve the quality of these devices and to decrease their production cost, it is necessary to use large-diameter wafers with high and uniform resistivity. Recent developments in the crystal growth technology of Czochralski silicon have enable to produce Czochralski silicon wafers with sufficient resistivity and with well-controlled, suitable concentration of oxygen. In addition, using Czoehralski silicon for substrate materials may offer economical benefits, First, Czoehralski silicon wafers might be cheaper than standard floating zone silicon wafers, Second, Czoehralski wafers are available up to diameter of 300 mm. Thus, very large area devices could be manufactured, which would entail significant saving in the costs, In this work, the conventional Czochralski silicon crystals were grown with higher oxygen concentrations using high pure polysilicon crystals. The silicon wafers were annealed by several steps in order to obtain saturated oxygen precipitation. In those wafers high resistivity over $5,000{\Omega}$ cm is kept even after thermal donor formation annealing.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.202-205
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• 2002

Polycrystalline silicon thin film transistors (poly-Si TFTs) are used in a wide variety of applications, and will figure prominently future high-resolution, high-performance flat panel display technology However, it was very difficult to fabricate high performance poly-Si TFTs at a temperature lower than 300$^{\circ}C$ for glass substrate. Conventional process on a glass substrate were limited temperature less than 600$^{\circ}C$ This paper proposes a high temperature process above 750$^{\circ}C$ using a flexible molybdenum substrate deposited hydrogenated amorphous silicon (a-Si:H) and than crystallized a rapid thermal processor (RTP) at the various temperatures from 750$^{\circ}C$ to 1050$^{\circ}C$. The high temperature annealed poly-Si film illustrated field effect mobility higher than 30 $\textrm{cm}^2$/Vs, achieved I$\sub$on//I$\sub$off/ current ratio of 10$^4$ and crystall volume fraction of 92%. In this paper, we introduce the new TFTs Process as flexible substrate very promising roll-to-roll process, and exhibit the properties of high temperature crystallized poly-Si Tn on molybdenum substrate.

• 대한전기학회논문지
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• 제33권6호
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• pp.203-211
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• 1984

MOS silicon solar cells have been developed using the fixed (interface) charge inherent to thermally oxidized silicon to induce an n-type inversion layer in 1-10 ohm-cm p-type silicon. Higher collection efficiencies are predicted than for diffused junction cells. Without special precautions a conversion efficiency of 14.2% is obtained. A MOS silicon solar cell is described in which an inversion layer forms the active area which is then contacted by means of a MOS grid. The highest efficiency is obtained when the resistivity of the substrate is high.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.42-45
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• 1992

The poly silicon thin films were prepared by solid phase crystallization at 600$^{\circ}C$ of amorphous silicon films deposited on Corning 7059 glass and (100) silicon wafer with thermally grown SiO$_2$substrate by plasma enhanced chemical vapor deposition with varying rf power, deposition temperature, total flow rate. Crystallization time, microstructure, absorption coefficients were investigated by RAMAN, XRD analysis and UV transmittance measurement. Crystallization time of amorphous silicon films was increased with increasing rf power, decreasing deposition temperature and decreasing total flow rate.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.153-153
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• 2009

We investigated the dependence of the memory margin of the Cap-less memory cell on the strain of top silicon channel layer and also compared kink effect of strained Cap-less memory cell with the conventional Cap-less memory cell. For comparison of the characteristic of the memory margin of Cap-less memory cell on the strain channel layer, Cap-less transistors were fabricated on fully depleted strained silicon-on-insulator of 0.73-% tensile strain and conventional silicon-on-insulator substrate. The thickness of channel layer was fabricated as 40 nm to obtain optimal memory margin. We obtained the enhancement of 2.12 times in the memory margin of Cap-less memory cell on strained-silicon-on-insulator substrate, compared with a conventional SOI substrate. In particular, much higher D1 current of Cap-less memory cell was observed, resulted from a higher drain conductance of 2.65 times at the kink region, induced by the 1.7 times higher electron mobility in the strain channel than the conventional Cap-less memory cell at the effective field of 0.3MV/cm. Enhancement of memory margin supports the strained Cap-less memory cell can be promising substrate structures to improve the characteristics of Cap-less memory cell.