• 한국표면공학회지
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• 제33권4호
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• pp.217-221
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• 2000

The gate oxide thickness is becoming thinner and thinner in order to speed up the semiconductor CMOS devices. We have investigated very thin$ SiO_2$ gate oxide layers and found anomaly between the thickness determined with capacitance measurement and these obtained with cross-sectional high resolution transmission electron microscopy. The thicknesses difference of the two becomes important for the thickness of the oxide below 5nm. We propose that the variation of dielectric constant in thin oxide films cause the anomaly. We modeled the behavior as (equation omitted) and determined $\varepsilon_{bulk}$=3.9 and $\varepsilon_{int}$=-4.0. We predict that optimum $SiO_2$ gate oxide thickness may be $20\AA$ due to negative contribution of the interface dielectric constant. These new results have very important implication for designing the CMOS devices.s.

• 한국전기전자재료학회논문지
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• 제16권12호
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• pp.1065-1070
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• 2003

HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.539-542
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• 2001

In SiC semiconductor device processing, it needs high temperature anneal for activation of ion implanted dopants. The macrosteps, 7~8nm in height, are formed on the surface of SiC substrates during activation anneal. We have investigated the effect of thermally-grown SiO$_2$layer on the suppression of macrostep formation during high temperature anneal. The cap oxide layer was found to be efficient for suppression of macrostep formation even though the annealing temperature is as high as the melting point of SiO$_2$. The thin cap oxide layer (10nm) was evaporated during anneal then the macrosteps were formed on SiC substrate. On the other hand the thicker cap oxide layer (50nm) remains until the anneal process ends. In that case, the surface was smoother and the macrosteps were rarely formed. The thermally-grown oxide layer is found to be a good material for the suppression of macrostep formation because of its feasibility of growing and processing. Moreover, we can choose a proper oxide thickness considering the evaporate rate of SiO$_2$at the given temperature.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.37-40
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• 1999

For the first time, charge trapping nonvolatile semiconductor memories with the deoxidized oxynitride gate dielectric is proposed and demonstrated. Gate dielectric wit thickness of less than 1 nm have been grown by postnitridation of pregrown thermal silicon oxides in NO ambient and then reoxidation. The nitrogen distribution and chemical state due to NO anneal/reoxidation were investigated by M-SIMS, TOF-SIMS, AES depth profiles. When the NO anneal oxynitride film was reoxidized on the nitride film, the nitrogen at initial oxide interface not only moved toward initial oxide interface, but also diffused through the newly formed tunnel oxide by exchange for oxygen. The results of reoxidized oxynitride(ONO) film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/N-rich SiON interface/Si-rich SiON(nitrogen diffused tunnel oxide)/Si substrate. In addition, the SiON and the S1$_2$NO Phase is distributed mainly near the tunnel oxide, and SiN phase is distributed mainly at tunnel oxide/Si substrate interface.

• 상하수도학회지
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• 제27권5호
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• pp.631-639
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• 2013

국내 하수처리장 인 방류기준이 강화되어 다양한 방법의 인 제거기술이 적용되고 있다. 흡착은 비교적 간단하면서 효과적으로 인을 제거할 수 있다. 본 연구에서는 흡착제인 Fe-Mn-Si oxide와 Fe-Mn oxide을 개발하여, 인 제거효율을 검토하였으며 이 흡착제에 대하여 Kinetic과 Isotherm모델을 비교하였다. 두 흡착제의 최대흡착양은 각각 47.8, 35.5 mg-$PO{_4}^{3-}/g$이었고, 이들은 낮은 pH에서 효과적으로 흡착하였다. Freundlish isotherm 모델이 Langmuir 모델보다 Fe-Mn-Si oxide의 흡착에 더 적합했다. 이온성 용액은 인이 흡착되는 과정에서 음이온들과 경쟁관계로 흡착능이 감소되었다. 비록 음이온과 humic물질들로부터 흡착에 영향을 받지만 Fe-Mn-Si oxide는 Fe-Mn oxide보다 흡착능이 크게 나타났다.

• E2M - 전기 전자와 첨단 소재
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• 제8권1호
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• pp.71-76
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• 1995

The thermal oxidation of Ge$_{0.2}$Si$_{0.8}$ in wet ambient has been investigated by Rutherford Backscattering Spectrometry(RBS). A uniform Ge$_{0.2}$Si$_{0.8}$O$_{2}$ oxide is formed at temperatures below 650.deg. C for polycrystalline and below 700.deg. C for single crystalline substrates. At higher temperatures Ge becomes depleted from the oxide and finally SiO$_{2}$ oxide is formed with Ge piled-ub behind it. The transition between the different oxide types depends also on the crystallinity of Ge$_{0.2}$Si$_{0.8}$. When a uniform Ge$_{0.2}$Si$_{0}$8/O$_{2}$ oxide grows, its thickness is proportional to the square root of the oxidation time, which suggests that the rate noting process is the diffusive transport of oxidant across the oxide. It is believed the oxidation is controlled by the competition between the diffusion of Ge or Si in Ge$_{0.2}$Si$_{0.8}$ and the movement of oxidation front.t.oxidation front.t.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.940-943
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• 2005

The characteristics of a-Si:H TFTs with silicon oxide as passivation layer were reported. It was studied that the insulating characteristics and step coverage characteristics of low temperature silicon oxide before applying to a-Si:H TFT fabrications. With the optimum deposition conditions considering electrical and deposition characteristics, low temperature silicon oxide was applied to a-Si:H TFTs. The changes in characteristics of a-Si:H TFTs were analyzed after replacing silicon nitride passivation layer with low temperature silicon oxide layer. This low temperature silicon oxide can be adapted to high resolution a-Si:H TFT LCD panels.

• 한국세라믹학회지
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• 제32권3호
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• pp.371-377
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• 1995

Silicon oxide films were grown on single-crystal silicon substrates at low temperatures (25~205$^{\circ}C$) in a low pressure electron cyclotron resonance (ECR) oxygen plasma. The growth rate of the silicon oxide film increased as the temperature increased or the pressure decreased. Also, the thickness of the silicon oxide film increased at negative bias voltage, but not changed at positive bias voltage. The growth law of the silicon oxide film was approximated to the parabolic form. Capacitance-voltage (C-V) and current density-electric field (J-E) characteristics were studied using Al/SiO2/p-Si MOS structures. For a 10.2 nm thick silicon oxide film, the leakage current density at the electric field of 1 MVcm-1 was less than 1.0$\times$10-8Acm-2 and the breakdown field was higher than 10 MVcm-1. The flat band voltage of Al/SiO2/p-Si MOS capacitor was varied in the range of -2~-3 V and the effective dielectric constant was 3.85. These results indicate that high quality oxide films with properties that are similar to those of thermal oxide film can be fastly grown at low temperature using the ECR oxygen plasma.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• 한국진공학회지
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• 제10권3호
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• pp.328-334
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• 2001

초박막 게이트 유전막 및 비휘발성 기억소자의 게이트 유전막으로 연구되고 있는 NO/$N_2$O 질화산화막 및 재산화질화산화막의 특성을 D-SIMS(dynamic secondary ion mass spectrometry), ToF-SIMS(time-of-flight secondary ion mass spectrometry), XPS(x-ray Photoelectron spectroscopy)으로 조사하였다. 시료는 초기산화막 공정후에 NO 및 $N_2$O 열처리를 수행하였으며, 다시 재산화공정을 통하여 질화산화막내 질소의 재분포를 형성토록 하였다. D-SIMS 분석결과 질소의 중심은 초기산화막 계면에 존재하며 열처리 공정에서 NO에 비해서 $N_2$O의 경우 질소의 분포는 넓게 나타났다. 질화산화막내 존재하는 질소의 상태를 조사하기 위하여 ToF-SIMS 및 XPS 분석을 수행한 결과 SiON, $Si_2$NO의 결합이 주도적이며 D-SIMS에서 조사된 질소의 중심은 SiON 결합에 기인한 것으로 예상된다. 재산화막/실리콘 계면근처에 존재하는 질소는 $Si_2$NO 결합형태로 나타나며 이는 ToF-SIMS로 얻은 SiN 및 $Si_2$NO 결합종의 분포와 일치하였다.