• Title/Summary/Keyword: Si MOSFET

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Low-frequency Noise Characteristics of Si0.8Ge0.2 pMOSFET Depending upon Channel Structures and Bias Conditions (채널구조와 바이어스 조건에 따른 Si0.8Ge0.2 pMOSFET의 저주파잡음 특성)

  • Choi Sang-Sik;Yang Hun-Duk;Kim Sang-Hoon;Song Young-Joo;Lee Nae-Eung;Song Jong-In;Shim Kyu-Hwan
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.1
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    • pp.1-6
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    • 2006
  • High performance $Si_{0.8}Ge_{0.2}$ heterostructure metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated using well-controlled delta-doping of boron and $Si_{0.8}Ge_{0.2}$/Si heterostructure epitaxal layers grown by reduced pressure chemical vapor deposition. In this paper, we report 1/f noise characteristics of the SiGe pMOSFETs measured under various bias conditions of the gate and drain voltages changing in linear operation regions. From the noise spectral density, we found that the gate and drain voltage dependence of the noise represented same features, as usually scaled with $f^{-1}$ However, 1/f noise was found to be much lower in the device with boron delta-doped layer, by a factor of $10^{-1}_10^{-2}$ in comparison with the device fabricated without delta-doped layer. 1/f noise property of delta-doped device looks important because the device may replace bipolar transistors most commonly embedded in high-frequency oscillator circuits.

Nonvolatile Memory Characteristics of Double-Stacked Si Nanocluster Floating Gate Transistor

  • Kim, Eun-Kyeom;Kim, Kyong-Min;Son, Dae-Ho;Kim, Jeong-Ho;Lee, Kyung-Su;Won, Sung-Hwan;Sok, Jung-Hyun;Hong, Wan-Shick;Park, Kyoung-Wan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.27-31
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    • 2008
  • We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

SiC Based Single Chip Programmable AC to DC Power Converter

  • Pratap, Rajendra;Agarwal, Vineeta;Ravindra, Kumar Singh
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.6
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    • pp.697-705
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    • 2014
  • A single chip Programmable AC to DC Power Converter, consisting of wide band gap SiC MOSFET and SiC diodes, has been proposed which converts high frequency ac voltage to a conditioned dc output voltage at user defined given power level. The converter has high conversion efficiency because of negligible reverse recovery current in SiC diode and SiC MOSFET. High frequency operation reduces the need of bigger size inductor. Lead inductors are enough to maintain current continuity. A complete electrical analysis, die area estimation and thermal analysis of the converter has been presented. It has been found that settling time and peak overshoot voltage across the device has reduced significantly when SiC devices are used with respect to Si devices. Reduction in peak overshoot also increases the converter efficiency. The total package substrate dimension of the converter circuit is only $5mm{\times}5mm$. Thermal analysis performed in the paper shows that these devices would be very useful for use as miniaturized power converters for load currents of up to 5-7 amp, keeping the package thermal conductivity limitation in mind. The converter is ideal for voltage requirements for sub-5 V level power supplies for high temperatures and space electronics systems.

Low-Frequency Noise Characteristics of SiGe pMOSFET Depending upon Channel Structures and Bias Conditions (SiGe pMOSFET의 채널구조와 바이어스 조건에 따른 잡음 특성)

  • Choi, Sang-Sik;Yang, Hun-Duk;Kim, Sang-Hoon;Song, Young-Joo;Cho, Kyoung-Ik;Kim, Jeonng-Huoon;Song, Jong-In;Shim, Kyu-Hwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.5-6
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    • 2005
  • High performance SiGe heterostructure metal-oxide-semiconductor field effect transistors(MOSFETs) were fabricated using well-controlled delta-doping of boron and SiGe/Si heterostructure epitaxal layers grown by reduced pressure chemical vapor deposition. In this paper, we report 1/f noise characteristics of the SiGe MOSFETs measured under various bias conditions of the gate and drain voltages changing in linear operation regions. From the noise spectral density, we found that the gate and drain voltage dependence of the noise represented same features, as usually scaled with $f^1$. However, 1/f noise was found to be much lower in the device with boron delta-doped layer, by a factor of $10^{-1}\sim10^{-2}$ in comparion with the device fabricated without delta-doped layer. 1/f noise property of delta-doped device looks important because the device may replace bipolar transistors most commonly embedded in high-frequency oscillator circuits.

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DC Characteristics of n-MOSFET with $Si_{0.88}Ge_{0.12}$ Heterostructure Channels ($Si_{0.88}Ge_{0.12}$ 이종접합 구조의 채널을 이용한 n-MOSFET의 DC 특성)

  • Choi, Sang-Sik;Yang, Hyun-Duk;Han, Tae-Hyun;Cho, Deok-Ho;Lee, Nae-Eung;Shim, Kyu-Hwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.150-151
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    • 2006
  • $Si_{0.88}Ge_{0.12}$/Si heterostructure channels grown by RPCVD were employed to n-type metal oxide semiconductor field effect transistors(MOSFETs), and their electrical properties were investigated. SiGe nMOSFETs presented very high transconductance compared to conventional Si-bulk MOSFETs, regardless substantial drawbacks remaining in subthreshold-slope, $I_{off}$, and leakage current level. It looks worthwhile to utilize excellent transconductance properties into rf applications requesting high speed and amplification capability, although optimization works on both device structure and unit processes are necessary for enhanced isolation and reduced power dissipation.

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Metal Plasma-Etching Damages of NMOSFETs with Pure and $N{_2}O$ Gate Oxides (게이트 산화막에 따른 nMOSFET의 금속 플라즈마 피해)

  • Jae-Seong Yoon;Chang-Wu Hur
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.3 no.2
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    • pp.471-475
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    • 1999
  • The metal plasma-etch damage immunity of nMOSFET with $N{_2}O$ gate oxide is found to be improved comparing to that with regular pure oxide of similar thickness. With increasing the antenna ratio (AR), the characteristics of nMOSFETs with $N{_2}O$ oxide shows tighter initial distribution and smaller degradation under constant field stress, which is explained by the effect of the nitrogen at the substrate $Si/SiO_2$ interface. Also, if $N{_2}O$ gate oxide is used, the maximum allowable size of metal AAR and PAR may be increased to the much larger values. These improvements of nMOSFETs with $N{_2}O$ gate oxide are attributed to the effect of the interface hardness improved by the nitrogen included at the substrate-Si/$N{_2}O$-oxide interface.

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Temperature reliability analysis according to the gate dielectric material of 4H-SiC UMOSFET (4H-SiC UMOSFET의 gate dielectric 물질에 따른 온도 신뢰성 분석)

  • Jung, Hang-San;Heo, Dong-Beom;Kim, Kwang-Su
    • Journal of IKEEE
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    • v.25 no.1
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    • pp.1-9
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    • 2021
  • In this paper, a 4H-SiC UMOSFET was studied which is suitable for high voltage and high current applications. In general, SiO2 is a material most commonly used as a gate dielectric material in SiC MOSFETs. However, since the dielectric constant value is 2.5 times lower than 4H-SiC, it suffers a high electric field and has poor characteristics in the SiO2/SiC junction. Therefore, the static characteristics of a device with high-k material as a gate dielectric and a device with SiO2 were compared using TCAD simulation. The results show BV decreased, VTH decreased, gm increased, and Ron decreased. Especially when the temperature is 300K, the Ron of Al2O3 and HfO2 decreases by 66.29% and 69.49%. and at 600K, Ron decreases by 39.71% and 49.88%, respectively. Thus, Al2O3 and HfO2 are suitable as gate dielectric materials for high voltage SiC MOSFET.

Hybrid High-efficiency Synchronous Converter using Si IGBT and SiC MOSFET

  • Il Yang;Woo-Joon Kim;Tuan-Vu Le;Seong-Mi Park;Sung-Jun Park;Ancheng Liu
    • Journal of the Korean Society of Industry Convergence
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    • v.26 no.6_1
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    • pp.967-976
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    • 2023
  • Currently, with the thriving development in the field of solar energy, the widespread adoption of solar grid-connected power conversion systems is rapidly expanding. As the market continues to grow, the efficiency of solar power conversion systems is steadily increasing, while prices are rapidly decreasing. Photovoltaic panels often produce low output voltages, and Boost converters are commonly employed to elevate and stabilize these voltages. They are also utilized for implementing Maximum Power Point Tracking (MPPT), ensuring the full utilization of solar power generation. Recently, synchronous control techniques have been introduced, using controllable switching devices like Si IGBT or SiC MOSFET to replace the diodes in the original circuits. However, this has raised concerns related to costs. This paper offers a compromise solution, considering both the performance and economic factors of the converter. It proposes a hybrid high-efficiency synchronous converter structure that combines Si IGBT and SiC MOSFET. Additionally, the proposed topology has been practically implemented and tested, with results confirming its feasibility and cost-effectiveness.

A Study on the Output Filter Design to meet NEMA Standard for a SiC MOSFET Inverter Fed Motor Drive Applications (전동기 구동용 SiC MOSFET 인버터의 NEMA 규격 만족을 위한 출력 필터 구조에 관한 연구)

  • Baek, Seunghoon;Cho, Younghoon;Cho, Byung-Geuk;Hong, Chanook
    • Proceedings of the KIPE Conference
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    • 2016.11a
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    • pp.53-54
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    • 2016
  • 본 논문은 전동기 구동용 SiC MOSFET 인버터의 NEMA(National equipment manufacturer's association) 규격 만족을 위한 출력 필터 구조에 따른 영향을 분석한다. 구조와 목적에 따라 정현파 필터와 dv/dt 필터를 적용하여 380V, 60Hz, 3.7kW급 유도 전동기를 대상으로 실험을 수행하여 설계한 필터가 NEMA 규격을 만족시킬 수 있을 뿐만 아니라 전동기 누설전류를 감소시켜 효율까지 향상시킬 수 있음을 확인하였다.

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High-precision Rogowski coil circuit design for SiC MOSFET short circuit detection (SiC MOSFET 단락 검출 회로를 위한 고정밀 Rogowski 코일 회로 설계)

  • Lee, Ju-A;Sim, Dong Hyeon;Son, Won-Jin;Ann, Sangjoon;Byun, Jongeun;Lee, Byoung Kuk
    • Proceedings of the KIPE Conference
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    • 2020.08a
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    • pp.196-198
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    • 2020
  • 본 논문은 SiC MOSFET의 단락 검출을 위한 고정밀 Rogowski 코일 회로 설계 방법을 제안한다. 설계 방법을 제안하기 위해 먼저 Rogowski 코일의 기본 구성인 적분기를 실제 시스템 요구 사양에 맞추어 설계한다. 설계한 회로의 성능 확인을 위하여 DPT (double pulse test)를 실시하며, test 결과 분석을 통해 문제점을 파악하고 전류 센싱 정밀도 향상을 위해 입출력 필터 설계 및 Rogowski 코일 턴 수를 변경한다. 변경한 각 조건들에 대하여 DPT를 진행하고 각 test 결과를 기반으로 Rogowski 코일 회로 설계 방안을 제안한다.

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