• Journal of the Korean Ceramic Society
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• v.38 no.10
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.3
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• pp.204-212
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• 2020

In this study, device suitability analysis is performed by comparing the performance of SiC MOSFET and GaN Transistor, which are WBG power semiconductor devices in the induction heating (IH) system. WBG devices have the advantages of low conduction resistance, switching losses, and fast switching due to their excellent physical properties, which can achieve high output power and efficiency in IH systems. In this study, SiC and GaN are applied to a general half-bridge series resonant converter topology to compare the conduction loss, switching loss, reverse conduction loss, and thermal performance of the device in consideration of device characteristics and circuit conditions. On this basis, device suitability in the IH system is analyzed. A half-bridge series resonant converter prototype using the SiC and GaN of a 650-V rating is constructed to verify device suitability through performance comparison and verified through an experimental comparison of power loss and thermal performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.658-660
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• 2004

In this paper, we have investigated electrical characteristics about doble gate MOSFET with changed oxide layer thickness of nam Sate and side gate, main gate and Si-substrate. We have known that optimum thickness of nam gate and side gate at 4nm, gate and Si-substrate at 3nm. We have applied for side gate voltage 3V, and drain voltage 1.5V. finally, we have known that importance of oxide layer thickness between main gate and Si-substrate better than main gate and side Sate.

• ETRI Journal
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• v.27 no.4
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.3
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• pp.540-544
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• 2017

In this study, we analyzed the effects of TID(Total Ionizing Dese) and TREE(Transient Radiation Effects on Electronics) on nMOSFET and pMOSFET fabricated by 0.18um CMOS process. The size of nMOSFET and pMOSFET is 100um/1um(W/L). The TID test was conducted up to 1 Mrad(Si) with a gamma-ray(Co-60). During the TID test, the nMOSFET generated leakage current proportional to the applied dose, but that of the pMOSFET was remained in a steady state. The TREE test was conducted at TEST LINAC in Pohang Accelerator Laboratory with a maximum dose-rate of $3.16{\times}10^8rad(si)/s$. In that test nMOESFET generated a large amount of photocurrent at a maximum of $3.16{\times}10^8rad(si)/s$. Whereas, pMOSFETs showed high TREE immunity with a little amount of photocurrent at the same dose rate. Based on the results of this experiment, we will progress the research of the radiation hardening for CMOS unit devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.415-419
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• 2014

나노스케일 MOSFET에서 leakage current는 중요한 이슈로서 $Si_{1-x}Ge_x$ alloy를 substrate로 사용할 경우 leakage current에 어떤 영향을 미칠 것인지 시뮬레이션을 통하여 알아보았다. $Si_{1-x}Ge_x$ alloy에서 Ge의 비율이 증가할수록 유효질량이 작아졌으나 conduction band minimum의 위치는 Si에 비해 상승하였다. 이로 인해 tunneling 확률이 증가하여 $Si_{1-x}Ge_x$ alloy를 substrate로 사용할 경우 leakage current를 더욱 증가시키게 되었다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.1
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• pp.9-13
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• 1982

The purpose of this experiment is to evaluate the noise dependency on the gate dimensions of the P-ch MOSFET which is fabricated of p+ sourse, drain, and gate electrode doped with PH$_3$ gas in type-N Si sudstrate. Experimental results indicate that: for the constant gate area and reletively thick films, noise level tends to decrease for the W/L ratio over unity, which generally conforms with theoretical observations, but its variation with the change in the thickness of film is less than the theoretically predicted for the W/L ratio below unity.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.2
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• pp.83-87
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• 2020

In this letter, we propose and analyze a new asymmetric structure that can be used for next-generation power semiconductor devices. We compare and analyze the electrical characteristics of the proposed device with respect to those of symmetric devices. The proposed device has a p-emitter on the right side of the cell. The peak electric field is reduced by the shielding effect caused by the p-emitter structure. Consequently, the breakdown voltage is increased. The proposed asymmetric structure has an approximately 100% higher Baliga's figure of merit (~94.22 MW/㎠) than the symmetric structure (~46.93 MW/㎠), and the breakdown voltage of the device increases by approximately 70%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.210-211
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• 2008

탄화규소를 이용한 600V급 MOSFET 소자 제작을 위하여 특성 simulation을 수행하였다. 600V 내압을 얻기 위해서 불순물 농도가 1E16/cm3이고 에피층의 두께가 6um인 상용 탄회규소 웨이퍼를 기준으로 하였으며 TRIM simulation을 사용하여 P-body의 retrograde profile을 구하고 이를 이용하여 소자의 전기적 특성을 simulation 하였다. P-body의 표면 농도를 5E16/cm3 에서 1E18/cm3으로 변화시키면서 소자의 전기적 특성을 예측하였으며 실험 결과와 비교하여 특성 변수를 추출하였다.