• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.97-100
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• 2008

정보화 사회가 진행되어감에 따라 카메라 센서, 디지털 카메라, 휴대폰, 영상 관련디지털 기기들이 증가하고 이로 인하여 영상정보 서비스 기술의 중요성이 크게 부각되었다. 특히 멀티미디어 응용서비스 기술에서는 영상 정보가 필수적인데, 그 영상 정보의 양이 너무 방대하여 압축 부호화를 하여 사용되고 있다. 본 논문에서는 정지영상압축 방법 중 JPEG표준에서 제시한 4가지 동작 모드 중 베이스라인을 기반으로 하는 JPEG압축 알고리즘을 연구하여 CMOS 이미지 센서에서 영상을 전송받으면 8*8 블록 단위로 변환 후 DCT 및 양자화 과정을 거쳐 지그재그 스캔을 한 후 허프만 코드를 사용하여 압축 부호화 시키는 JPEG 베이스라인 인코더를 VHDL언어로 설계하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.198-206
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• 2011

This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with $0.18-{\mu}m$ BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.59-59
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• 2009

The efficiency of CMOS technology has been developed in uniform rate. However, there was a limitation of reducing the thickness of Gate-oxide since the thickness of Gate Dielectric is also reduced so an amount of leakage current is grow. In order to solve this problem, the semiconductor device which has a dual gate is used widely. This paper presents a method and a necessity for making the Gate Stack of TFT. Before Using test devices to measure values, stacking $SiN_x$ on a wafer test was conducted.

• ETRI Journal
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• v.31 no.5
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• pp.622-624
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• 2009

This letter presents a compact 2.5 Gb/s burst-mode receiver using the first reported monolithic amplifier IC developed with 0.25 ${\mu}m$ SiGe BiCMOS technology. With optimum avalanche photodiode gain, the receiver module can obtain a fast response, high sensitivity and wide dynamic range, satisfying the overhead timing and various power specifications for a 2.5 Gb/s next-generation passive optical network (PON), as well as a legacy 1.25 Gb/s PON in the upstream.

• Electronics and Telecommunications Trends
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• v.31 no.6
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• pp.1-12
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• 2016

GaN 전력반도체는 와이드 밴드갭(Eg=3.4eV)과 높은 이동도 및 낮은 온-저항 특성으로 인하여 차세대 고속/저손실 고효율 전력반도체 소자로서 각광을 받고 있다. 그럼에도 불구하고 글로벌 GaN 전력반도체 기술개발과 상용화는 초기단계로 선진업체 캐치업과 추월이 가능한 분야이다. GaN 반도체의 재료적 장점과 현재 상용화된 200V 이하급과 650V급 GaN 전력반도체 소자의 글로벌 시장동향으로 볼 때 고속 스위칭과 전력모듈 소형화 및 시스템의 고효율화를 요구하는 제품응용에 특화해야할 것으로 판단된다. 특히 기존 Si 전력반도체 대비 고성능 GaN 제품의 저가격화뿐만 아니라 선진기업과의 경쟁력 확보를 위하여 6인치 기반 Au-free CMOS 호환 공정 개발을 통한 GaN 전력반도체 기술의 국산화와 신시장 선점을 위한 조기 상용화의 중요성을 강조하고자 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.100-106
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• 1999

A new IBC(Island Body Contact) structure is introduced to SOI CMOS VLSI for stabilizing the body potential of the MOSFET without the additional area consumption. The improvement of the body contact effect is achieved by reducing the body resistance and the area is saved as the bodies of the MOSFETs are connected together. Its property as VLSI device is confirmed through the device simulations and the measurement.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1305-1308
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• 2008

In this study, we redesigned the reliable integrated on-panel display gate driver that was equipped with dual pull-down as well as controlled discharge-path structure to reduce the high voltage stress effect and realized with TSMC 0.35 um CMOS-based technology before. An improved discharge path and a low noise design are proposed for our new a-Si TFT process implementation. Our novel reliable gate driver design can make each cell of shift register to be insensitive to the coupling noise of that stage.

• Proceedings of the KSME Conference
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• 2003.11a
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• pp.1932-1938
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• 2003

We have applied spectroscopic ellipsometry to investigate $high-{\kappa}$ dielectric thin films and correlate their optical properties with fabrication processes, in particular, with high temperature annealing. The use of high-k dielectrics such as $HfO_{2}$, $Ta_{2}O_{5}$, $TiO_{2}$, and $ZrO_{2}$ as the replacement for $SiO_{2}$ as the gate dielectric in CMOS devices has received much attention recently due to its high dielectric constant. From the characteristics found in the pseudo-dielectric functions or the Tauc-Lorentz dispersions, the optical properties such as optical band gap, polycrystallization, and optical density will be discussed.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.325-328
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• 2002

We developed a high performance 2.2" active matrix OLED display for IMT-2000 mobile phone. Scan and Data driver circuits were integrated on the glass substrate, using low temperature poly-Si(LTPS) TFT CMOS technology. High efficiency EL materials were employed to the panel for low power consumption. Peak luminescence of the panel was higher than 250cd/$m^2$ with power consumption of 200mW.