JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

  • Received : 2011.10.06
  • Published : 2012.09.30
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Abstract

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

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References

  1. X. Wu, P. Palmers, M. S. J. Steyaert, "A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC," IEEE J. Solid-State Circuits, pp. 2396-2403, Nov. 2008.
  2. A. V. d. Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, "A 10-bit 1-GSamples Nyquist current-steering CMOS D/A converter," IEEE J. Solid-State Circuits, pp. 315-324, May. 2001.
  3. J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE J. Solid-State Circuits, pp. 1959-1969, Dec. 1998.
  4. G. A. M. V. D. Plas, J. Vandenbussche, M. S. J. Steyaert, W. Sansen, and G. G. E. Gielen, "A 14-bit intrinsic accuracy $Q^2$ random walk CMOS DAC," IEEE J. Solid-State Circuits, pp. 1708-1718, Dec. 1999.
  5. Min-Jung Kim, Hyuen-Hee Bae, Jin-Sik Yoon, and Seung-Hoon Lee, "A 3V 12b 100MS/s CMOS D/A Converter for High-Speed Communication Systems," Journal of Semiconductor Technology and Science, pp. 211-216, Dec. 2003.
  6. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, pp. 1433-1439, Oct. 1989.
  7. A. V. d. Bosch, M. S. J. Steyaert, and W. Sansen, "SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters," in Proc. 6th IEEE Int. Conf. Electronics, Circuits and Systems, pp. 1193-1196, Sep. 1999.
  8. B. Razavi, Principals of Data Conversion System Design, New York: IEEE Press 1995.
  9. M. Tiilikainen, "A 14-bit 1.8-V 20-mW 1-$mm^2$ CMOS DAC," IEEE J. Solid-State Circuits, pp. 1144-1147, July. 2001.
  10. J. J. Jung, B. H. Park, S. S. Choi, S. I. Lim, and S. Kim, "A 6-bit 2.704Gsps DAC for DS-CDMA UWB," IEEE Asia Pacific Circuits and Systems, pp. 347-350, Dec. 2006.

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