• The Transactions of the Korea Information Processing Society
• /
• v.1 no.2
• /
• pp.272-278
• /
• 1994

The paper proposes a test pattern generator and a signature analyzer for pseudoexhaustive testing of the combinational circuit part within a sequential circuit when performing built-in self test of the circuit. The test pattern generator can scan in the seed test pattern and generate exhaustive test patterns. The signature analyzer can perform the analysis of the circuit response and scan out the result. Such test pattern generator and signature analyzer have been developed using SRL(shift register latch) and LFSR(linear feedback shift register).

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.3
• /
• pp.26-33
• /
• 1984

This paper proposes a new LSI/VLSI logic design structure which improves shift register latches in conventional LSSD. Test patterns are easily generated and fault coverage is enhanced by using the design structure. The new parallel shift register latch can be applied to the design of easily testable PLA's. In this case, the number of test patterns is decreased and decoders which are added to the feedback inputs in conventional PLA's using LSSD are not necessary.

• The KIPS Transactions:PartC
• /
• v.8C no.1
• /
• pp.12-15
• /
• 2001

A summation generator creates sequence from addition with carry of LFSR (Linear Feedback Shift Register) sequences. Similarly, it is possible to generate keystream by bitwise exclusive-oring on two FCSR sequences. In this paper, we described the cryptographic properties of a sequence generated by the FCSRs.

• Journal of Korea Society of Industrial Information Systems
• /
• v.8 no.3
• /
• pp.85-90
• /
• 2003

This paper proposes a modular multiplier based on LFSR (Linear Feedback Shift Register) architecture with efficient area complexity over GF(2/sup m/). At first, we examine the modular exponentiation algorithm and propose it's architecture, which is basic module for public-key cryptosystems. Furthermore, this paper proposes on efficient modular multiplier as a basic architecture for the modular exponentiation. The multiplier uses AOP (All One Polynomial) as an irreducible polynomial, which has the properties of all coefficients with '1 ' and has a more efficient hardware complexity compared to existing architectures.

• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.1931_1933
• /
• 2009

NoC 기반 시스템이 적용되는 설계는 시스템 크기가 커짐에 따라 칩 테스트 문제도 동시에 제기 되고 있다. 이에 따라 NoC 기반의 시스템의 테스트 시간을 줄일 수 있는 internal test 방식의 새로운 BIST(Built-in Self-Test) 구조에 관한 연구를 하였다. 기존의 NoC 기반 시스템의 BIST 테스트 구조는 각각의 router와 core에 BIST logic과 random pattern generator로 LFSR(Linear Feedback Shift Register)을 사용하여 연결하는 individual 방식과 하나의 BIST logic과 LFSR을 사용하여 각각의 router와 core에 병렬로 연결하는 distributed 방식을 사용한다. 이때, LFSR에서 생성된 테스트 벡터가 router에 사용되는 FIFO 메모리를 통과하면서 생기는 테스트 타임 증가를 줄이기 위하여 shift register 형태의 FIFO 메모리를 변경하였다 제안된 방법에서 테스트 커버리지 98%이상을 달성하였고, area overhead면에서 효과를 볼 수 있다.

• Proceedings of the KIEE Conference
• /
• 1987.07b
• /
• pp.1476-1480
• /
• 1987

This paper proposes a design method for SCLA(sequential CMOS Domino Logic Array) using 1-level CMOS Domino Logic and Stable Shift Register Latch. Also an algorithm to generate a test sequence and a test procedure for the SCLA are presented. The SCLA has advantages of low power consumption, high density and high speed, and performs hazard-and race-free logic operation, because of using SSRL(Stable Shift Register Latch). By using the proposed test method, all of stuck-at, cross-point, stuck-on and stuck-open faults in SCLA are detected by short test sequence.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.7C
• /
• pp.915-920
• /
• 2004

In this paper, we propose the new polyphase sequence with the best nonperiodic autocorrelation property in the viewpoint of the merit factors, which are important criteria for a nonperiodic autocorrelation property. We propose the general implementation of a polyphase sequence generator over an integer residue ring by using a linear feedback shift register(LFSR), in addition, we analyze the linear complexities of polyphase sequences based on the proposed implementation method.

• 한국HCI학회:학술대회논문집
• /
• 2007.02a
• /
• pp.790-795
• /
• 2007

최근 유비쿼터스 컴퓨팅에 대한 연구가 활발히 진행되고 있으며 유비쿼터스 컴퓨팅의 실현을 위한 핵심기술로서 RFID 시스템에 대한 연구가 활발히 진행되고 있다. 유비쿼터스 환경에서 RFID 시스템이 사용자의 편리함을 가져다 주는 장점이 있는 반면, 이로 인해 사용자의 프라이버시가 침해 당할 수 있는 문제점 또한 가지고 있다. 본 논문에서 사용자 인증 알고리즘은 새로운 해쉬 함수를 사용하고 그리고 메시지 암호화를 위한 스트림 암호기는 LFSR(Linear Feedback Shift Register)을 사용한다.

• Journal of the Korean Chemical Society
• /
• v.25 no.2
• /
• pp.103-109
• /
• 1981

An inexpensive, yet convenient analog storage device was constructed. Sequentially MOSFET-switched 20 sample and holds equipped with a high input impedance preamplifier were parallelly matched to the digitally controlled shift register system in variable speeds up to 3 kHz. To verify its usefulness, square wave train, sinusiodal wave and some electrochemical data, such as fast-scan voltammogram and transient current-time curves of differential pulse polarography were tested.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.3
• /
• pp.707-714
• /
• 2010

Since an LFSR(linear feedback shift register) as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG(pseudo random pattern generator).