Journal of Korea Society of Industrial Information Systems (한국산업정보학회논문지)
- Volume 8 Issue 3
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- Pages.85-90
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- 2003
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- 1229-3741(pISSN)
Design of an LFSR Multiplier with Low Area Complexity
효율적인 공간 복잡도의 LFSR 곱셈기 설계
Abstract
This paper proposes a modular multiplier based on LFSR (Linear Feedback Shift Register) architecture with efficient area complexity over GF(2/sup m/). At first, we examine the modular exponentiation algorithm and propose it's architecture, which is basic module for public-key cryptosystems. Furthermore, this paper proposes on efficient modular multiplier as a basic architecture for the modular exponentiation. The multiplier uses AOP (All One Polynomial) as an irreducible polynomial, which has the properties of all coefficients with '1 ' and has a more efficient hardware complexity compared to existing architectures.
본 논문에서는 GF(2
Keywords