Design and Test of Sequential CMOS Domino Logic Array

순서 CMOS Domino Logic Array의 설계 및 테스트

This paper proposes a design method for SCLA(sequential CMOS Domino Logic Array) using 1-level CMOS Domino Logic and Stable Shift Register Latch. Also an algorithm to generate a test sequence and a test procedure for the SCLA are presented. The SCLA has advantages of low power consumption, high density and high speed, and performs hazard-and race-free logic operation, because of using SSRL(Stable Shift Register Latch). By using the proposed test method, all of stuck-at, cross-point, stuck-on and stuck-open faults in SCLA are detected by short test sequence.