• 센서학회지
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• 제3권2호
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• pp.74-80
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• 1994

Silicon direct bonding 기술은 잔류 응력이 없고, 안정한 특성을 가진 센서의 제작과 silicon-on-insulator 소자의 제조에 널리 이용되고 있다. SDB의 공정 절차는 크게 실리콘 웨이퍼의 수산화 공정 과정과 wet oxidation fumace에서 고온의 열처리 공정 과정을 거치게 된다. 수산화 공정을 행한 후, Fourier transformation-infrared spectroscopy를 사용하여 실리콘 웨이퍼 표면을 분석하여 보면, 실리콘 웨이퍼의 표면에서는 수산화기가 생성됨을 알 수 있다. 실험 결과, $H_{2}O_{2}\;:\; H_{2}SO_{4}$ 용액을 사용한 친수성 용액 처리의 경우에 있어서는 수산화기가 3474 $cm^{-1}$ 주위의 넓은 영역에서 관찰되었다. 그러나, diluted HF 용액의 경우에 있어서는 수산화기가 관찰되지 않았다. 접합된 실리콘웨이퍼를 tetramethylammonium hydroxide 식각 용액을 사용하여 식각 공정을 수행하였다. 식각 공정은 자동 식각 중지가 수행되었으며, 식각된 표면은 평탄하고 균일하였다. 그러므로, 이러한 SDB 기술은 우수한 특성을 가진 압력, 유속, 가속도 센서 등과 같은 센서의 제작 및 센서 응용 분야에 이용될 수 있을 것이다.

• 한국전기전자재료학회논문지
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• 제13권6호
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• pp.514-519
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$as a dielectrical isolation layer a SDB SOI Hall sensor without pn junction has been fabricated on the Si/ $SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to 30$0^{\circ}C$ the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm$6.7$\times$10$_{-3}$ and $\pm$8.2$\times$10$_{-4}$$^{\circ}C$ respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 영호남학술대회 논문집
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• pp.29-33
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than ${\pm}6.7{\times}10^{-3}/^{\circ}C$ and ${\pm}8.2{\times}10^{-4}/^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.565-568
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm 6.7$$\times$$10^{-3}$/$^{\circ}C$ and $\pm 8.2$$\times$$10^{-4}$/$^{\circ}C$respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and hip high-temperature operation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1431-1433
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• 1995

This paper describes the characteristics of Si Hall sensors fabricated on a SOI(Si-on-insulator} structure, in which the SOI structure was forrmed by SDB(Si-wafer direct bonding) technology. The Hall voltage and the sensitivity of implemented Si Hall devices show good linearity with respect to the applied magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall device is average $600V/A{\cdot}T$. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(Temperature Coefficient of the Offset Voltage) and TCS(Temperature Coefficient of the product Sensitivity) are less than ${\pm}6.7{\times}10^{-3}/^{\circ}C$ and ${\pm}8.2{\times}10^{-4}/^{\circ}C$, respectively. From these results, Si Hall sensors using the SOI structure presented here are very suitable for high-temperature operation.

• 센서학회지
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• 제3권1호
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• pp.19-25
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• 1994

KOH와 같은 이방성 식각수용액를 사용하여 직각모양의 볼록한 가장자리를 식각할 때, 언더컷팅에 의해 가장 자리가 뭉개어지는 현상이 나타난다. 그래서 이 현상을 방지하기 위해 mass 패턴을 수정할 필요가 있어 보상법에 관한 실험을 하였다. 가속도센서 소자공간을 고려할 경우 정사각형의 보상구조로 mass를 보상하는 것이 적당하다는 결과를 얻었다. 이 결과를 기초로, SDB 웨이퍼를 이용하여 사각뿔 형태의 mass 보상된 실리콘 압저항형 가속도센서를 제조하였다.

• 한국전기전자재료학회논문지
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• 제13권12호
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• pp.977-982
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• 2000

Conventional transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area. These consequently have disadvantage for high speed switching performance. In this paper, a lateral structure transistor which has minimized parasitic capacitance by using SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics are designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance is proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed lateral structure transistor is certified through the V$\_$CE/-I$\_$C/ characteristics curve, h$\_$FE/-I$\_$C/ characteristics, and GP-plot. Cutoff Frequency is 13.7㎓.

• 센서학회지
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• 제13권3호
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• pp.175-181
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• 2004

A pressure sensor for high temperature was fabricated by using a SDB(Silicon-Direct-Bonding) wafer with a Si/$SiO_{2}$/ Si structure. High pressure sensitivity was shown from the sensor using a single crystal silicon of the first layer as a piezoresistive layer. It also was made feasible to use under the high temperature as of over $120^{\circ}C$, which is generally known as the critical temperature for the general silicon sensor, by isolating the piezoresistive layer dielectrically and thermally from the silicon substrate with a silicon dioxide layer of the second layer. The pressure sensor fabricated in this research showed very high sensitivity as of $183.6{\mu}V/V{\cdot}kPa$, and its characteristics also showed an excellent linearity with low hysteresis. This sensor was usable up to the high temperature range of $300^{\circ}C$.

• 한국전기전자재료학회논문지
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• 제14권4호
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• pp.263-268
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• 2001

This paper describes the effects of applied bias conditions on electrochemical etch-stop characteristics. THere are a number of key issues such as diode leakage and ohmic losses which arise when applying the conventional 3-electrochemical etch-stop to fabricated some of he MEMS(microelectro mechanical system) and SOI(Si-on-insulator) structures which employ SDB(Si-wafer direct bonding). This work allows to perform anin situ diagnostic to predict whether or not an electrochemical etch-stop would fail due to diode-leakage-induced premature passivation. In addition, it presents technology which takes into account the effects of ohmic losses and allows to calculate the appropriate bias necessary to obtain a successful electrochemical etch-stop.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.759-762
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• 2000

Present transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area, consequently have disadvantage for high speed switching performance. In this paper, a horizontal structure transistor which has minimized parasitic capacitance in virtue of SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics were designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance was proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed horizontal structure transistor was certified through the VCE-lC characteristics curve, $h_{FE}$ -IC characteristics, and GP-plot.