• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.123-136
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• 2006

The prefetching technique is an effective way to reduce the latency caused memory access. However, excessively aggressive prefetch not only leads to cache pollution so as to cancel out the benefits of prefetch but also increase bus traffic leading to overall performance degradation. In this thesis, a prefetch filtering scheme is proposed which dynamically decides whether to commence prefetching by referring a filtering table to reduce the cache pollution due to unnecessary prefetches In this thesis, First, prefetch hashing table 1bitSC filtering scheme(PHT1bSC) has been shown to analyze the lock problem of the conventional scheme, this scheme such as conventional scheme used to be N:1 mapping, but it has the two state to 1bit value of each entries. A complete block address table filtering scheme(CBAT) has been introduced to be used as a reference for the comparative study. A prefetch block address lookup table scheme(PBALT) has been proposed as the main idea of this paper which exhibits the most exact filtering performance. This scheme has a length of the table the same as the PHT1bSC scheme, the contents of each entry have the fields the same as CBAT scheme recently, never referenced data block address has been 1:1 mapping a entry of the filter table. On commonly used prefetch schemes and general benchmarks and multimedia programs simulates change cache parameters. The PBALT scheme compared with no filtering has shown enhanced the greatest 22%, the cache miss ratio has been decreased by 7.9% by virtue of enhanced filtering accuracy compared with conventional PHT2bSC. The MADT of the proposed PBALT scheme has been decreased by 6.1% compared with conventional schemes to reduce the total execution time.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.42-49
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• 2000

In this paper, we propose the parallel ternary logic circuit design algorithm to DCG Property with 2$^n$ nodes. To increase circuit integration, one of the promising approaches is the use of multiple-valued logic(MVL). It can be useful methods for the realization of compact integrated circuit, the improvement of high velocity signal processing using parallel signal transmission and the circuit design algorithm to optimize and satisfy the circuit property. It is all useful method to implement high density integrated circuit. In this paper, we introduce matrix equation to satisfy given DCG with 2$^n$ nodes, and propose the parallel ternary logic circuit design process to circuit design algorithm. Also, we propose code assignment algorithm to satisfy for the given DCG property. According to the simulation result of proposed circuit design algorithm, it have the following advantage ； reduction of the circuit signal lines, computation time and costs.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.93-98
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• 2003

With the improvement of digital signal processors, digital pulse compressor(DPC) is widely used in radar systems. The DPC can be implemented by using FIR filter algorithm in time domain or FFT algorithm in frequency domain. This paper designs an expansible DPC using multiple DSPs. With ADSP-21060 of Analog Devices Inc., the computation time as a function of the number of received range cells and FIR filter tap is compared and analyzed in time domain using C-language and assembly language. therefore, when radar system parameters are determined, the number of DSP's required to implement DPC can be easily estimated.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.6
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• pp.55-59
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• 2008

For effective mobility control of UGV(unmanned ground vehicle), the terrain cover classification is an important component as well as terrain geometry recognition and obstacle detection. The vision based terrain cover classification algorithm consists of pre-processing, feature extraction, classification and post-processing. In this paper, we present a method to classify terrain covers based on the color and texture information. The color space conversion is performed for the pre-processing, the wavelet transform is applied for feature extraction, and the SVM(support vector machine) is applied for the classifier. Experimental results show that the proposed algorithm has a promising classification performance.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.95_96
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• 2009

In this paper, a new algorithm of Integrated Volt/Var Control (IVVC) is proposed using Volt/Var control for the Distribution Automation System (DAS) based on the modeling of the distributed load and the distributed current. In the proposed, the load flow based on the modeling of the distributed load with Distributed Generation and the distributed current are estimated from constants of four terminals using the measurement of the current and power factor from a Feeder Remote Terminal Unit (FRTU). For Integrated Volt/Var Control (IVVC), the gradient method is applied to find optimal solution for tap and capacity control of OLTC (On-Load Tap Changers), SVR (Step Voltage Regulator), and SC (Shunt Condenser). What is more Volt/Var control method is proposed using moving the tie switch as well as IVVC algorithm using power utility control. In the case studies, the estimation and simulation network have been testified in Matlab Simulink.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.6
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• pp.27-32
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• 2010

77GHz FMCW(Frequency Modulation Continuous Wave) radar system has been used for automotive active safety systems. In typical automotive radar, the moving target detection and clutter cancellation including stationary targets are very important signal processing algorithms. This paper proposed the moving target detection algorithm which improve the detection probability and reduce the false alarm rate. First, the proposed moving target beat-frequency extraction filter is used in order to suppress clutter, and then the data association is applied by using the extracted moving target beat-frequency. Then, the zero-Doppler target is eliminated to remove the rest of clutter.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.35-41
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• 2000

In this paper, the multiplicative algorithm of two polynomals over finite field GF(2$^{m}$ ) is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. This multiplier is consisted of three operation unit: multiplicative operation unit, the modular operation unit, the primitive irreducible operation unit. The multiplicative operation unit is composed of AND gate, X-OR gate and multiplexer. The modular operation unit is constructed by AND gate, X-OR gate. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and interconnection of the cells are regular, well-suited for VLSI realization.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.36-42
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• 2002

In this paper, we proposed a multiplicative algorithm for two polynomials with all non-zero coefficients over finite field GF($P^m$). Using the proposed multiplicative algorithm, we constructed the multiplier of modular architecture with parallel in-output. The proposed multiplier is composed of $(m+1)^2$ identical cells, each cell consists of one mod(p) additional gate and one mod(p) multiplicative gate. Proposed multiplier need one mod(p) multiplicative gate delay time and m mod(p) additional gate delay time not clock. Also, our architecture is regular and possesses the property of modularity, therefore well-suited for VLSI implementation.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2003.05a
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• pp.217-224
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• 2003

ISO 14649 is a new interface (or language) standard for the CAD-CAM -CNC chain, currently under establishment by ISO TC184 SCI and SC4 . Upon completion, it will replace ISO 6983, so called M amp; G codes used for CNC since 1950' s. As the new language is being established, a new CNC controller called STEP-CNC (STEP­compliant CNC), capable of carrying out various intelligent tasks using the new language as an input, receives worldwide attention. In this paper, we present a distributed architecture for STEP-NC system based on the generic paradigm of STEP-NC. The STEP-NC system is consisted of 3 sub-systems: 1) CGS (Code Generation System), 2) CES (Code Edit System), and 3) ACS (Autonomous Control System). Also presented in this paper is algorithm for delta volume decomposition, a crucial algorithm for developing CGS. First method is based on the cutting tool and the second method is based on the turning features commonly used in the shop floor. An illustrative example is given to compare the two methods, and to illustrate usage scenario of the delta volume in the turning STEP- NC system under development.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.4
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• pp.39-43
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• 2004

A typical theme of active vision systems is gaze-fixing of a camera. Here gaze-fixing of a camera means by steering orientation of a camera so that a given point on the object is always at the center of the image. For this we need to combine a function to analyze image data and a function to control orientation of a camera. This paper presents an algorithm for gaze-fixing of a camera where image analysis and orientation control are designed in a frame. At this time, for avoiding difficulties in implementing and aiming for real-time applications we design the algorithm to be a simple closed-form without using my information related to calibration of the camera or structure estimation.