• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.1025-1028
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• 1999

After detecting the edge which is applying the morphological operators to the hybrid FCNN, we could analyze and compare. The hybrid FCNN is completely removed to the noise in the image, and worked in order to obtain the result image which is closest to the original image. Also, the morphological operator is applied to the image as the method in order to detect more good the edge than the conventional edge. FCNN which is the pipeline type is completely suitable to detecting the image processing as well as the hardware size. In this paper. we would make the structure elements of the morphological operator the variable template and the static template, and compare with the edge enhancement of two images. After being the result which is applying the variable template morphological operator and the static template morphological operator to the image, we could know that the edge images applying the variable template is superior in a edge enhancement side.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.914-917
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• 1999

The paper describes a 17 $\times$ 17-b multiplier using the Radix-4 Booth’s algorithm. which is suitable for 32-bit RISC/DSP microprocessors. To minimize design area and achieve improved speed, a 2-stage pipeline structure is adopted to achieve high clock frequency. Each part of circuit is modeled and optimized at the transistor level, verification of functionality and timing is performed using HSPICE simulations. After modeling and validating the circuit at transistor level, we lay it out in a 0.35 ${\mu}{\textrm}{m}$ 1-poly 4-metal CMOS technology and perform LVS test to compare the layout with the schematic. The simulation results show that maximum frequency is 330MHz under worst operating conditions at 55$^{\circ}C$ , 3V, The post simulation after layout results shows 187MHz under worst case conditions. It contains 9, 115 transistors and the area of layout is 0.72mm by 0.97mm.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.257-260
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• 1999

We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.

• The Bulletin of The Korean Astronomical Society
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• v.35 no.2
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• pp.38.1-38.1
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• 2010

We present the results of the survey for submillimeter galaxies in the MS0451 (04h 54m 10.8s, -03d 00m 57.0s) at z = 0.55 and PKS1138-262 (11h 40m 48.25s, -26d 29m 10.1s) at z = 2.16 with the 1.1mm bolometer array AzTEC at the James Clerk Maxwell Telescope. The samples were centered on a prominent large-scale structure overdensity. Submillimeter galaxies seem to be starburst galaxies at high redshift ($z\;\geq\;1$) with high starformation rates ($\sim1000M\odot\;yr^{-1}$) or active galactic nuclei (AGN). We have obtained AzTEC images using the AzTEC data reduction pipeline with the IDL language. Through a bayes' theorem, we determined the extragalaxy catalogue, containing the false-detection rate, completeness, flux deboosting correction, and the source positional uncertainty in this region. We compared the catalogue with HST, DSS, 2MASS observations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.37-45
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• 1998

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2275-2276
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• 2008

Currently the quarter prediction giga it is used SE3208 from EISC ISA [1]] where it does in base. But the prediction which is perfect is difficult improved Pipeline structures and PC the structure which is not Delay to add it decided. Even PC and IF/ID blocks, the area and expense were added, but Bubble without it will be able to control Conditional Branch doors and the possibility of decreasing a help in processor performance improvements.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.38-40
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• 2007

In this paper, we propose a novel architecture, which is based on DCT (Discrete Cosine Transform), for ME (Motion Estimation) and MC (Motion Compensation). The traditional algorithms of ME and MC based on DCT did not suffer the advantage of the coarseness of the 2-dimensional DCT (2-D DCT) coefficients to reduce the operational time. Therefore, we derive a recursion equation for transform-domain ME and MC and design the structure by using highly regular, parallel, and pipeline processing elements. The main difference with others is removing the IDCT block by using to transform domain. Therefore, the performance of our algorithm is more efficient in practical image processing such as DVR (Digital Video Recorder) system. We present the simulation result which is compare with the spatial domain methods. it shows reducing the calculation cost. compression ratio. and peak signal to noise ratio (PSNR).

• Journal of Korea Multimedia Society
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• v.20 no.11
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• pp.1803-1810
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• 2017

A large amount of processing time is required if the process of detecting the touch position on the touch screen and displaying it on the display panel is performed only by software. In this paper, we propose a method to output information touched on the screen using H/W method in order to improve the response speed delay. In the FPGA module designed for the HDMI signal output to the display module, the touch information is input to the serial data signal including touch coordinate information, point size, and color information. Then the module render the image using HDMI signal input to the module and the touch information. This method has a pipeline structure so it has effect of reducing the delay time that occurs in outputting the touch information compared with the conventional software processing method.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.657-660
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• 2002

In this paper, the FFT processor for power measurement using VHDL (Very high-speed integrated circuit Hardware Description Language) is discussed. The proposed system relies on the FFT algorithm to compute real and reactive power. The advantage of system is that harmonic analysis is carried out on a period of the Input signal. The proposed system is based on FFT Processor which is designed using VHDL. In the design of FFT processor, $radix-2^2$ is adopted to reduce several complex multipliers for twiddle factor. And this processor adopt pipeline structure. Therefore, the system Is able to have both high hardware efficiency and high performance.

• Genomics & Informatics
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• v.9 no.4
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• pp.189-193
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• 2011

Simple sequence repeats (SSRs) are ubiquitous short tandem duplications found within eukaryotic genomes. Their length variability and abundance throughout the genome has led them to be widely used as molecular markers for crop-breeding programs, facilitating the use of marker-assisted selection as well as estimation of genetic population structure. Here, we report a software application, "SSR-Primer Generator " for SSR discovery, SSR-primer design, and homology-based search of in silico amplicons from a DNA sequence dataset. On submission of multiple FASTA-format DNA sequences, those analyses are batch processed in a Java runtime environment (JRE) platform, in a pipeline, and the resulting data are visualized in HTML tabular format. This application will be a useful tool for reducing the time and costs associated with the development and application of SSR markers.