Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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EISC pipelineing optimizations for processor speed improvements

EISC processor의 속도 향상을 위한 pipelineing 최적화

  • Son, Mu-Chang (School of Information&Communication Engineering, Sungkyunkwan University) ;
  • Kim, In-Soo (School of Information&Communication Engineering, Sungkyunkwan University) ;
  • Min, Hyoung-Bok (School of Information&Communication Engineering, Sungkyunkwan University) ;
  • Lee, Young-Geol (Division of Computer Science and Information, Daelim College)
  • 손무창 (성균관대학교 정보통신공학부) ;
  • 김인수 (성균관대학교 정보통신공학부) ;
  • 민형복 (성균관대학교 정보통신공학부) ;
  • 이영걸 (대림대학 컴퓨터정보계열)
  • Published : 2008.07.16
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Abstract

Currently the quarter prediction giga it is used SE3208 from EISC ISA [1]] where it does in base. But the prediction which is perfect is difficult improved Pipeline structures and PC the structure which is not Delay to add it decided. Even PC and IF/ID blocks, the area and expense were added, but Bubble without it will be able to control Conditional Branch doors and the possibility of decreasing a help in processor performance improvements.

Keywords