• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.8 no.4
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• pp.38-45
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• 1994

It is very imprtant and necessary to predict luminous enviroment in an interior space. This paper has de scribed about energy saving and evaluated interior visual environment in a office building having on/off turning control lighting system utilizing daylight. In order to predict the interior varior illumination distribution, the scale model w a m~a de and examined under various conditions, such ad difference of window glass, and color pattern of wall, floor, and also ceiling lighting system type. Ths paper suggests that basic fundamental data of lighting design ~rformancein the concept and schematic stages of design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1152-1160
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• 2003

Start The current paper proposes an improved HD(High Definition) monitor that can support a signal input with various resolutions. Due to the inadequate performance of the built-in digital PLL(Phase-locked Loop) of an ADC(Analog to Digital Converter) and poor tolerance of ADC ICs, there are problems in the stable processing of synchronization signals with various input signals. Accordingly, the proposed synchronization signal optimization technique regenerates the horizontal synchronization signal in the vertical blanking interval based on the regularity of the synchronization signal, i.e. the timing of the falling edge signal remains constant, thereby solving the above problem and minimizing the interference of the system. As a result, the proposed system can stabilize various synchronization signals with different resolution modes.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1199-1201
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• 2002

Today, the ceramic transformer becomes widely used for the TFT LCD backlight inverter system thanks to its high efficiency and small size. In this paper, a high efficient inverter system for cold cathode flourescent lamp (CCFL) including PLL controller for tuning the PWM frequency to the frequency that the efficiency of the inverter system becomes maximum is proposed. The control IC implementing this feature will be released by Interpion Co. Ltd. in May 2002.

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.2
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• pp.79-84
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• 2007

This papar reports design and fabrication of CMOS temperature control circuit using MOSIS 0.25um-3.3V CMOS technology. The proposed circuit has a temperature coefficient of $13mV/^{\circ}C$ for a wide operating temperature range with a good linearity. Furthermore, the temperature coefficient of output voltage can be controlled by adjusting external bias voltage. This circuit my be applicable to the design of one-chip IC where quartz crystal resonator is mounted on CMOS oscillator chips.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.12
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• pp.1644-1651
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• 1995

A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.50-56
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• 2015

An efficient fast response hysteretic buck converter suitable for mobile application is propoesed. The problems of large output ripple and difficulty in using of small power inductor that conventional hysteretic converter has are improved by adding ramp generator. and the changeable switching frequency with load current is fixed by adding a delay time control circuit composed of PLL structure resulting in decrease of EMI noise. The circuits are implemented by using BCDMOS 0.35um 2-polt 4-metal process. Measurement results show that the converter operates with a switching frequency of 1.85MHz when drives 80mA load current. As the converter drives over 170mA load current, the switching frequency is fixed on 2MHz. The converter has output ripple voltage of less 20mV and more than efficiency 85% with 50~500mA laod current condition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.100-105
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• 2010

In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.5
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• pp.677-684
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• 2021

This paper presents a time-to-digital converter for measuring absolute time differences. The time-to-digital converter was designed and fabricated in 0.18-um CMOS technology and it can be applied to Light Detection and Ranging system which requires long time-cover range and 50ps time resolution. Since designed time-to-digital converter adopted the reference clock of 625MHz generated by phase locked loop, it could have absolute time resolution of 50ps after automatic calibration and its cover range was over than 800ns. The time-to-digital converter adopted a counter and chain delay lines for time measurement. The counter is used for coarse time measurement and chain delay lines are used for fine time measurement. From many times experiments, fabricated time-to-digital converter has 50 ps time resolution with maximum INL of 0.8 LSB and its power consumption is about 70 mW.