• Journal of Korean Society of Water and Wastewater
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• v.23 no.5
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• pp.599-608
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• 2009

This manuscript covers the results of field investigation and lab-scale experiments to design a double-layered biofilter system to control urban storm runoff. The biofilter system consisted of a coarse soil layer (CSL) for filtration and fine soil layer (FSL) for adsorption and biological degradation. The variations of flow rate and water quality of runoff from a local expressway were monitored for seven storm events. Laboratory column experiments were performed using seven kinds of soil and mulch to maximize pollutants removal. The site mean concentration (SMC) of storm runoff from the drainage area (runoff coefficient: 0.92) was measured to be 203 mg/L for SS, 307 mg/L for $TCOD_{Cr}$, 12.3 mg/L for TN, 7.3 mg/L for ${NH_4}^+-N$, and 0.79 mg/L for TP, respectively. This study employed a new design concept, to cover the maximum rainfall intensity with one month recurrence interval. Effective storms for last ten years (1998-2007) in seoul suggested the design rainfull intensity to be 8.8 mm/hr Single layer soil column showed the maximum removal rate of pollutants load when the uniformity coefficient of CSL was 1.58 and the silt/clay contents of FSL was virtually 7%. The removal efficiency during operation of double layer soil column was 98% for SS and turbidity, 75% for TCODCr, 56% for ${NH_4}^+-N$, 87% for TP, and 73-91% for heavy metals. The hydraulic conductivity of the soil column, 0.023 cm/sec, suggested that the surface area of the biofilter system should be about 1% of the drainage area to treat the rainfall intensity of one month recurrence interval.

• Journal of the Korean Ceramic Society
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• v.34 no.1
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• pp.88-94
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• 1997

The oxidation behavior of the NiCrAlY bond coat and thermal fatigue failure in the plasma-sprayed thermal barrier coating system, ZrO2.8wt%Y2O3 top coat/Ni-26Cr-5Al-0.5Y bond coat/Hastelloy X superalloy substrate, in commercial use for finned segment of gas turbine burner were investigated. The main oxides formed in the bond coat were NiO, Cr2O3, and Al2O3. It divided the oxide distribution at this interface into two types whether an Al2O3 thin layer existed beneath ZrO2/bond coat interface before operation at high temperature or not. While a continuous layer of NiO was formed mainly in the region where the Al2O3 thin layer was present, the absence of it resulted in the formation of mixture of Cr2O3 and Al2O3 beneath NiO layer. Analyses on the fracture surface of specimen spalled by thermal cycling showed that spalling occurred mainly along the ceram-ic coat near ZrO2/bond coat oxide layer interface, but slightly in the oxide layer region.

• Membrane Journal
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• v.16 no.3
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• pp.188-195
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• 2006

The purpose of this study was to investigate the effect of an intermittent aeration mode to reduce the membrane fouling in a submerged membrane process using the specifically devised module (YEF 750D-2). The fluid velocity on the module increased with increasing the supplied air volume, and decreased with the increment of MLSS in the biological reactor. The reduction rate of the fluid velocity was found to be $3\times10^{-4}m{\cdot}min/sec{\cdot}L$ per 1,000 mg MLSS/L increased. In the operation of the intermittent aeration, the intermitted stop of the aeration provoked the formation of a cake layer on the gel layer which was previously formed during the aeration, resulting in the highly increased TMP level. However, the TMP level could be significantly lowered by the subsequent backwashing and aeration that effectively removed the cake along with the gel layer on the membrane surface. In this study, the optimum condition for the intermittent aeration was determined to be aeration for 20 sec and pause for 20 sec.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.110.1-110.1
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• 2012

Recently, advances in ZnO based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). However, the electrical performances of oxide semiconductors are significantly affected by interactions with the ambient atmosphere. Jeong et al. reported that the channel of the IGZO-TFT is very sensitive to water vapor adsorption. Thus, water vapor passivation layers are necessary for long-term current stability in the operation of the oxide-based TFTs. In the present work, $Al_2O_3$ and $TiO_2$ thin films were deposited on poly ether sulfon (PES) and $SnO_x$-based TFTs by electron cyclotron resonance atomic layer deposition (ECR-ALD). And enhancing the WVTR (water vapor transmission rate) characteristics, barrier layer structure was modified to $Al_2O_3/TiO_2$ layered structure. For example, $Al_2O_3$, $TiO_2$ single layer, $Al_2O_3/TiO_2$ double layer and $Al_2O_3/TiO_2/Al_2O_3/TiO_2$ multilayer were studied for enhancement of water vapor barrier properties. After thin film water vapor barrier deposited on PES substrate and $SnO_x$-based TFT, thin film permeation characteristics were three orders of magnitude smaller than that without water vapor barrier layer of PES substrate, stability of $SnO_x$-based TFT devices were significantly improved. Therefore, the results indicate that $Al_2O_3/TiO_2$ water vapor barrier layers are highly proper for use as a passivation layer in $SnO_x$-based TFT devices.

• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.939-942
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• 2016

One of the most important characteristic curves of a solar cell is its current density-voltage (J-V) curve under AM1.5G insolation. Solar cell can be considered as a semiconductor diode, so a diode equivalent model was used to estimate its parameters from the J-V curve by numerical simulation. Active layer plays an important role in operation of a solar cell. We investigated the effect thicknesses and defect densities (N_d) of the active layer on the J-V curve. When the active layer thickness was varied (for N_d = 8×10¹⁷ cm^-3) from 800 nm to 100 nm, the reverse saturation current density (J_o) changed from 3.56×10^-5 A/cm² to 9.62×10^-11 A/cm² and its ideality factor (n) changed from 5.28 to 2.02. For a reduced defect density (N_d = 4×10¹⁵ cm^-3), the n remained within 1.45≤n≤1.92 for the same thickness range. A small increase in shunt resistance and almost no change in series resistance were observed in these cells. The low reverse saturation current density (J_o = 9.62×10^-11 A/cm²) and diode ideality factor (n = 2.02 or 1.45) were observed for amorphous silicon based solar cell with 100 nm thick active layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.240.2-240.2
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• 2013

The device scale of flash memory was confronted with quantum mechanical limitation. The next generation memory device will be required a break-through for the device scaling problem. Especially, graphene is one of important materials to overcome scaling and operation problem for the memory device, because ofthe high carrier mobility, the mechanicalflexibility, the one atomic layer thick and versatile chemistry. We demonstrate the hybrid memory consisted with the metal-oxide quantum dots and the mono-layered graphene which was transferred to $SiO_2$ (5 nm)/Si substrate. The 5-nm thick secondary $SiO_2$ layer was deposited on the mono-layered graphene by using ultra-high vacuum sputtering system which base pressure is about $1{\times}10^{-10}$ Torr. The $In_2O_3$ quantum dots were distributed on the secondary $SiO_2$2 layer after chemical reaction between deposited In layer and polyamic acid layer through soft baking at $125^{\circ}C$ for 30 min and curing process at $400^{\circ}C$ for 1 hr by using the furnace in $N_2$ ambient. The memory devices with the $In_2O_3$ quantum dots on graphene monolayer between $SiO_2$ thin films have demonstrated and evaluated for the application of next generation nonvolatile memory device. We will discuss the electrical properties to understating memory effect related with quantum mechanical transport between the $In_2O_3$ quantum dots and the Fermi level of graphene layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Journal of IKEEE
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• v.25 no.3
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• pp.467-472
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• 2021

Stable operation of semiconductor devices is needed even at high temperatures. Among the structures of semiconductor devices, the area that can cause unstable electrical responses at high temperatures is the contact layer between the metal and the semiconductor. In this study, the effect of annealing conditions included in the process of forming a contact layer of nickel silicide(NiSix) on a p-type SiC layer on the specific contact resistance of the contact layer and the total resistance between the metal and the semiconductor was investigated. To this end, a series of electrodes for TLM (transfer length method) measurements were patterned on the 4 inch p-type SiC layer under conditions of changing annealing temperature of 1700 and 1800 ℃ and annealing time of 30 and 60 minutes. As a result, it was confirmed that the annealing conditions affect the resistance of the contact layer and the electrical stability of the device.

• Korean Journal of Metals and Materials
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• v.49 no.10
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• pp.811-817
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• 2011

In this study, we have investigated the role of a metal oxide hole injection layer (HIL) between an Indium Tin Oxide (ITO) electrode and an organic hole transporting layer (HTL) in organic light emitting diodes (OLEDs). Nickel Oxide films were deposited at different deposition times of 0 to 60 seconds, thus leading to a thickness from 0 to 15 nm on ITO/glass substrates. To study the influence of NiO film thickness on the properties of OLEDs, the relationships between NiO/ITO morphology and surface properties have been studied by UV-visible spectroscopy measurements and AFM microscopy. The dependences of the I-V-L properties on the thickness of the NiO layers were examined. Comparing these with devices without an NiO buffer layer, turn-on voltage and luminance have been obviously improved by using the NiO buffer layer with a thickness smaller than 10 nm in OLEDs. Moreover, the efficiency of the device ITO/NiO (< 5 nm)/NPB/$Alq_3$/ LiF/Al has increased two times at the same operation voltage (8V). Insertion of a thin NiO layer between the ITO and HTL enhances the hole injection, which can increase the device efficiency and decrease the turn-on voltage, while also decreasing the interface roughness.

• The KIPS Transactions:PartD
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• v.19D no.2
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• pp.161-186
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• 2012

Recently, the flash memory consistently increases the storage capacity while the price of the memory is being cheap. This makes the mass storage SSD(Solid State Drive) popular. The flash memory, however, has a lot of defects. In order that these defects should be complimented, it is needed to use the FTL(Flash Translation Layer) as a special layer. To operate restrictions of the hardware efficiently, the FTL that is essential to work plays a role of transferring from the logical sector number of file systems to the physical sector number of the flash memory. Especially, the poor performance is attributed to Erase-Before-Write among the flash memory's restrictions, and even if there are lots of studies based on the log block, a few problems still exists in order for the mass storage flash memory to be operated. If the FAST based on Log Block-Based Flash often is generated in the wide locality causing the random writing, the merge operation will be occur as the sectors is not used in the data block. In other words, the block thrashing which is not effective occurs and then, the flash memory's performance get worse. If the log-block makes the overwriting caused, the log-block is executed like a cache and this technique contributes to developing the flash memory performance improvement. This study for the improvement of the random writing demonstrates that the log block is operated like not only the cache but also the entire flash memory so that the merge operation and the erase operation are diminished as there are a distinct mapping table called as the offset mapping table for the operation. The new FTL is to be defined as the XAST(extensively-Associative Sector Translation). The XAST manages the offset mapping table with efficiency based on the spatial locality and temporal locality.