• Journal of Korea Society of Industrial Information Systems
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• v.19 no.6
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• pp.1-6
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• 2014

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of low speed, high area overhead or high wire complexity. Therefore, this paper proposes a new high-speed NCL gate cells designed at transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate cells have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.59-65
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• 2013

Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.4
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• pp.17-23
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• 2012

Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.209-213
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• 2017

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.112-118
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• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.1
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• pp.53-59
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• 2017

This Paper Proposes a New High-speed Design Methodology for Delay Insensitive Asynchronous Circuits Combining with a Pseudo-NMOS Structure used for High Performance in Synchronous Circuits. Null Convention Logic(NCL) of Conventional Delay-Insensitive Asynchronous Design Methodologies has many Advantages of High Reliability, Low Power Consumption, and Easy Design Reuses not Dependant on Semiconductor Technology. However. the Conventional NCL Gates has a Complicated Stack Structure, so it Suffers from Increased Circuit Delay. Therefore, a New NCL Gates and its Pipeline Structure for High Performance, and the Proposed Methodology has been Designed and Evaluated by a $4{\times}4$ Multiplier Designed using SK-Hynix 0.18 um CMOS Technology. The Experimental Results are Compared with a Conventional NCL in Terms of Power and Delay and shows that the Propagation Delay of the Proposed Multiplier is Reduced by 85% Compared with the Conventional NCL Multiplier.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.1
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• pp.61-67
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• 2014

Conventional synchronous circuits in low power required systems such as sensor systems cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in the reliable ultra-low power design, asynchronous circuits have recently been reconsidered as a solution for scaling issues. However, it is not easy to totally replace synchronous circuits with asynchronous circuits in the digital systems, so the interfacing between the synchronous and asynchronous circuits is indispensable for the digital systems. This paper presents a new design for interfacing between asynchronous circuits and synchronous circuits, and the interface circuits are applied to a $4{\times}4$ multiplier logic designed using 0.11um technology.