• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.419-427
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• 2016

In this paper, a 64b small-area MTP memory IP is designed. A VPPL (=VPP/3) regulator and a VNN (=VNN/3) charge pump are removed since the inhibit voltages of an MTP memory cell are all 0V instead of the conventional voltages of VPP/3 and VNN/3. Also, a VPP charge pump is removed since the VPP program voltage is supplied from an external pad. Furthermore, a VNN charge pump is designed to provide its voltage of -VPP as a one-stage negative charge pump using the VPP voltage. The layout size of the designed 64b MTP memory IP with MagnaChip's $0.18{\mu}m$ BCD process is $377.585{\mu}m{\times}328.265{\mu}m$ (=0.124mm2). Its DC-DC converter related layout size is 76.4 percent smaller than its conventional counterpart.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

• Journal of IKEEE
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• v.28 no.1
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• pp.78-89
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• 2024

PMIC chips based on a BCD process used in automotive semiconductors require multi-time programmable (MTP) intellectual property (IP) that does not require additional masks to trim analog circuits. In this paper, MTP cell size was reduced by about 18.4% by using MTP cells using PMOS capacitors (PCAPs) instead of NMOS capacitors (NCAPs) in MTP cells, which are single poly EEPROM cells with two transistors and one MOS capacitor for small-area MTP IP design. In addition, from the perspective of MTP IP circuit design, the two-stage voltage shifter circuit is applied to the CG drive circuit and TG drive circuit of MTP IP design, and in order to reduce the area of the DC-DC converter circuit, the VPP (=7.75V), VNN (=-7.75V) and VNNL (=-2.5V) charge pump circuits using the charge pumping method are placed separately for each charge pump.

• Smart Structures and Systems
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• v.11 no.3
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• pp.261-282
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• 2013

Structural health monitoring (SHM) is an application area of Wireless Sensor Networks (WSNs) which usually needs high data communication rate to transfer a large amount of monitoring data. Traditional sink node can only process data from one communication channel at the same time because of the single radio chip structure. The sink node constitutes a bottleneck for constructing a high data rate SHM application giving rise to a long data transfer time. Multi-channel communication has been proved to be an efficient method to improve the data throughput by enabling parallel transmissions among different frequency channels. This paper proposes an 8-radio integrated sink node design method based on Field Programmable Gate Array (FPGA) and the time synchronization mechanism for the multi-channel network based on the proposed sink node. Three experiments have been performed to evaluate the data transfer ability of the developed multi-radio sink node and the performance of the time synchronization mechanism. A high data throughput of 1020Kbps of the developed sink node has been proved by experiments using IEEE.805.15.4.

• Nuclear Engineering and Technology
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• v.55 no.2
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• pp.484-492
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• 2023

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

• Journal of Sensor Science and Technology
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• v.17 no.5
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• pp.387-395
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• 2008

An optic module system is developed adopting multiple colorimetry units for the measurement of multi-pad urinalysis dipsticks. Multiple photometry system instead of moving mechanisms has the advantages of system reliability and simplicity as well as economic aspects due to the recent development of economic color light emitting diodes and stable photo sensors. An integration amplifier with programmable integration time, a current source circuit with selectable and stable current settings were connected through analog multiplexers to thirty light emitting diodes for illumination and ten photo transistors for reading each strip pad. All the circuits are controlled by a microprocessor through a simple set of serial communication commands. The detect ability is eighteen times better than the minimum color difference of the test grading which is 0.013 in urobilinogen in the color space defined in this paper.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.215-220
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• 2005

Nowadays, various speech processing systems are being introduced in the fields of robotics. However, real-time processing and high performances are required to properly implement speech processing system for the autonomous robots. Achieving these goals requires advanced hardware techniques including intelligent software algorithms. For example, we need nonlinear amplifier boards which are able to adjust the compression radio (CR) via computer programming. And the necessity for noise reduction, double-buffering on EPLD (Erasable programmable logic device), simultaneous multi-channel AD conversion, distant sound localization will be explained in this paper. These ideas can be used to improve distant and omni-directional speech recognition. This speech processing system, based on embedded Linux system, is supposed to be mounted on the new home service robot, which is being developed at KIST (Korea Institute of Science and Technology)

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.9
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• pp.124-129
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• 2009

Recently, PWM inverter is widely utilized for many industrial applications such as high performance drive and space vector pulse width modulation(SVPWM) inverter which has high voltage ratio and low harmonics compared to conventional PWM inverter. This paper presents the implementation on a field programmable gate array(FPGA) of a SVPWM module for a voltage source inverter. The SVPWM module consists of PWM generator, current and position sensor interface and dead time compensator. The implemented SVPWM module can be integrated with a digital signal processor(DSP) to provide a flexible and effective solution for high performance voltage source inverter and for the use of multi-motor control. The performance of SVPWM module is verified by simulation and several experimental results.

• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.304-310
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• 2011

The application of time-domain methods in emission measurement instruments allows for a reduction in scan time by several orders of magnitude and for new evaluation methods to be realized such as the real-time spectrogram to characterize transient emissions. In this paper two novel systems for time-domain EMI measurements above 1 GHz are presented. The first system combines ultra-fast analog-to-digital-conversion and real-time digital signal processing on a field-programmable-gate-array (FPGA) with ultra-broadband multi-stage down-conversion to enable measurements in the range from 10 Hz to 26 GHz with high sensitivity and full-compliance with the requirements of CISPR 16-1-1. The required IF bandwidths were added to allow for measurements according to MIL-461F and DO-160F. The second system realizes a system of time-interleaved analog-to-digital converters (ADCs) and has an upper bandwidth limit of 4 GHz. With the implementation of an automatic mismatch calibration, the system fulfills CISPR 16-1-1 dynamic range requirements. Measurements of the radiated emissions of electronic consumer devices and household appliances like the non-stationary emissions of a microwave oven are presented. A measurement of a personal computer's conducted emissions on a power supply line according to DO-160F is given.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.5
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• pp.11-18
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• 2021

The small radio frequency tracking radar is a tracking system with a radio frequency sensor that identifies a target through all-weather radio frequency signal processing for a target and searches, detects and tracks the target for the major target. In this paper, we describe the development of a board equipped with TMS320C6678 and XILINX FPGA (Field Programmable Gate Array), a high-speed multi-core DSP that acquires target information through all-weather radio frequency and identifies a target through real-time signal processing. We propose DSP-FPGA combination architecture for DSP and FPGA selection and signal processing, and also explain the design of SRIO for high-speed data transmission.