• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.3
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• pp.206-213
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• 2022

This paper presents setting up a laboratory-scale testbed to estimate the aging of power MOSFET devices and integrated power modules by measuring its on-state voltage and current. Based on the aging mechanisms of the component inside the power module (e.g., bond-wire, solder layer, and semiconductor chip), a system to measure the on-state resistance of device-under-test (DUT) is designed and experimented: a full-bridge circuit applies current stress to DUT, and a temperature chamber controls the ambient temperature of DUT during the aging test. The on-state resistance of SiC MOSFET measured by the proposed testbed was increased by 2.5%-3% after 44-hour of the aging test.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.1031-1032
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• 2010

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.7-12
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• 2008

In this study, the wide width effect that the increasing rate of drain current and the value of cutoff frequency decrease with larger finger number is observed. For modeling this effect, an improved SPICE MOSFET RF model that finger number-independent external source resistance is connected to a conventional BSIM3v3 RF model is developed. Better agreement between simulated and measured drain current and cutoff frequency at different finger number is obtained for the improved model than the conventional one, verifying the accuracy of the improved model for $0.13{\mu}m$ multi-finger MOSFET.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.169-175
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• 2020

This paper studied the SET situation in VLSI because the electronic devices exposed to SET can indicate irregular operation and output errors. The SET environment was established using the exponential static wave (iexp) in the fold-cascode comparator. The comparator was experimented with how it affected it by the SET. In a folded comparator that did not enter the SET situation, the propagation delay was measured at 0.26㎲ and the gain was 0.649. The MOSFET close to the output stage was measured sensitively in the folded comparator that entered the SET situation. And propagation delay was calculated from 0.36 to 0.37㎲ and the gain was 0.649. The mid-position MOSFET was calculated from 0.28 to 0.30㎲ and the gain was 0.649. The MOSFET, which is farthest from the output stage from the folded comparator, was calculated with the propagation delay between 0.25 and 0.26㎲ and the gain of 0.649. In SET situations, the MOSFET close to the output portion of the folded comparator was sensitive. And at the MOSFET far from the output, the same results were obtained as a normal folded comparator without the SET input.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.1-6
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• 2010

In this paper, RF Capacitance-Voltage(C-V) curve of short-channel MOSFET has been extracted from the room temperature to $225^{\circ}C$ using a RF method based on measured S-parameter data, and its high-temperature dependent characteristics are empirically modeled. It is observed that the voltage shift according to the variation of temperature in the weak inversion region of RF C-V curves is lower than the threshold voltage shift, but it is confirmed that this phenomenon is unexplainable with a long-channel theoretical C-V equation. The new empirical equation is developed for high-temperature dependent modeling of short-channel MOSFET C-V curves. The accuracy of this equation is demonstrated by observing good agreements between the modeled and measured C-V data in the wide range of temperature. It is also confirmed that the channel capacitance decreases with increasing temperature at high gate voltage.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.163-168
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• 2010

This paper presents the practical implementation of an over-temperature protection system for power semiconductor devices. In the proposed system, temperature variation is provided with just using $R_{ds(on)}$ characteristics of power MOSFET, while extra device such as a temperature sensor or an over-temperature detection transistor is needed to monitor the temperature in the conventional method. The proposed protection technique is experimentally tested on IRF840 power MOSFET. The PIC microcontroller PIC16F877A is used for the implementation of the proposed protection algorithm. The built-in 10-bit A/D converter is utilized for detecting voltage variance between a drain and a source of IRF840. The induced temperature-resistance relationship based on the measured drain-source voltage, supplies a gate signal to the power MOSFET. If detected temperature's voltage exceeds any a protection temperature's voltage, the microcontroller removes the trigger signal from the power MOSFET. These test results showed satisfactory performances of the proposed protection system in term of accuracy within 1.5%.

• Journal of IKEEE
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• v.20 no.3
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• pp.220-225
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• 2016

In this paer, low on-resistance and high-power trench gate MOSFET (Metal-Oxide-Silicon Field Effect Transistor) incorporating current sensing FET (Field Effect Transistor) is proposed and evaluated. The trench gate power MOSFET was fabricated with $0.6{\mu}m$ trench width and $3.0{\mu}m$ cell pitch. Compared with the main switching MOSFET, the on-chip current sensing FET has the same device structure and geometry. In order to improve cell density and device reliability, self-aligned trench etching and hydrogen annealing techniques were performed. Moreover, maintaining low threshold voltage and simultaneously improving gate oxide relialility, the stacked gate oxide structure combining thermal and CVD (chemical vapor deposition) oxides was adopted. The on-resistance and breakdown voltage of the high density trench gate device were evaluated $24m{\Omega}$ and 100 V, respectively. The measured current sensing ratio and it's variation depending on the gate voltage were approximately 70:1 and less than 5.6 %.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.363-366
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• 1998

25.deg. C 에서 120.deg. C까지 온도를 증가시키면서 hot carrier effect에 의한 nMOSFET의 degradation을 drain current와 transconductance의 변화를 통해 알아보았다. 온도가 증가할수록 hot carrier에 의한 degradation 이 전체적으로 줄어드는 것을 볼수 있었다. stress를 가한 후 reverse mode로 측정하였는데 saturation 영역보다 linear 영역에서 drain current의 degradation이 크게 나탔으며 온도가 증가할수록 이러한 경향이 유지되면서 degradation이 감소하였다. transconductance는 linear 영역과 saturation 영역에서 각각 측정하였는데 온도가 증가할수록 linear 영역의 degradation이 더많이 감소하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.9-14
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• 2005

This paper reports the hot carrier induced RF performance degradation of bulk dynamic threshold voltage MOSFET (B-DTMOS) compared with bulk MOSFET (B-MOS). In the normal and moderate mode operations, the degradations of cut-off frequency $(f_{T})$ and minimum noise figure $(F_{min})$ of B-DTMOS are less significant than those of B-MOS devices. Our experimental results show that the RF performance degradation is more significant than the U performance degradation after hot carrier stressing. Also, the degradation characteristics of RF power Performance of B-DTMOS due to hot carrier effects are measured for the first time.