• 한국통신학회논문지
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• 제35권7C호
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• pp.587-593
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• 2010

본 논문에서는 extrinsic information transfer (EXIT) chart를 이용하여 다중 안테나 시스템에서 irregular low-density parity-check (LDPC) code를 설계하는 방법을 기술한다. 다중 안테나 기반의 Irregular LDPC code 설계를 위하여 maximum a posteriori probability (MAP) 방식의 다중 안테나 검출 방식이 사용되었으며 수신기는 다중 안테나 검출기와 LDPC 복호기 사이에서 복호된 soft 정보를 주고 받는 turbo iterative 구조를 가정하였다. 다중 안테나 기반의 irregular LDPC code의 edge degree 분포는 EXIT chart와 linear optimization programming 기법을 사용하여 얻을 수 있으며 컴퓨터 시뮬레이션을 통하여 제안된 방법으로 설계된 irregular LDPC code의 성능을 다양한 환경에서 검증하였다.

• Journal of Communications and Networks
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• 제11권5호
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• pp.455-463
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• 2009

We consider the challenges of finding good puncturing patterns for rate-compatible low-density parity-check code (LDPC) codes over additive white Gaussian noise (AWGN) channels. Puncturing is a scheme to obtain a series of higher rate codes from a lower rate mother code. It is widely used in channel coding but it causes performance is lost compared to non-punctured LDPC codes at the same rate. Previous work, considered the role of survived check nodes in puncturing patterns. Limitations, such as single survived check node assumption and simulation-based verification, were examined. This paper analyzes the performance according to the role of multiple survived check nodes and multiple dead check nodes. Based on these analyses, we propose new algorithm to find a good puncturing pattern for LDPC codes over AWGN channels.

• ETRI Journal
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• 제46권3호
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• 한국통신학회논문지
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• 제37권1A호
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• pp.34-42
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• 2012

LDPC(low density parity check) 부호는 낮은 복잡성과 Shannon의 한계에 근접하는 오류 정정 능력을 보이기 때문에 turbo 부호와 함께 많은 응용 분야에 적용되고 있다. 최근에는 분산 동영상 부호화(distributed video coding: DVC) 시스템의 Wyner-Ziv 프레임 복호를 위해서도 LDPC 부호가 많이 사용되고 있다. 본 논문에서는 DVC 시스템을 위한 LDPC 부호를 설계하기 위해 패리티 체크 행렬 H를 설계하고 부호율 적응적인(rate adaptive) 특성을 만족하기 위해 H 행렬의 패리티 점검 노드를 효율적으로 병합하는 방법을 제안한다. 이를 위해 cycle의 연결성을 고려한 ACE(approximation cycles EMD) 알고리즘을 기반으로 효율적인 LDPC 부호를 설계하고 부호율 적응적인 특성을 갖도록 하기 위해 H 행렬의 크기와 압축율을 고려하여 병합 범위를 지정하고 지정된 범위에 따라 패리티 점검 노드를 병합한다. 그리고 ACE 알고리즘의 계수와 차수 분포를 변화시키면서 설계한 LDPC 부호의 성능을 해석한다.

• Journal of Communications and Networks
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• 제13권3호
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• pp.205-210
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• 2011

This paper presents an approach to the construction of multiple-rate quasi-cyclic low-density parity-check (LDPC) codes. Parity-check matrices of the proposed codes consist of $q{\times}q$ square submatrices. The block rows and block columns of the parity-check matrix correspond to the hyperplanes (${\mu}$-fiats) and points in Euclidean geometries, respectively. By decomposing the ${\mu}$-fiats, we obtain LDPC codes of different code rates and a constant code length. The code performance is investigated in term of the bit error rate and compared with those of LDPC codes given in IEEE standards. Simulation results show that our codes perform very well and have low error floors over the additive white Gaussian noise channel.

• 한국통신학회논문지
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• 제32권3C호
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• pp.205-215
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• 2007

This paper presents low latency and/or computation algorithms of iterative codes of turbo codes, turbo product codes and low density parity check codes for use in wireless broadband communication systems. Due to high coding complexity of iterative codes, this paper focus on lower complexity and/or latency algorithms that are easily implementable in hardware and further accelerate the decoding speed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.161-162
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• 2008

In this paper we design an irregular low-density parity-check (LDPC) code for a multi-input multi-output (MIMO) system. The considered MIMO system is minimum mean square error soft-interference cancellation (MMSE-SIC) detector. The MMSE-SIC detector and the LDPC decoder exchange soft information and consist a turbo iterative detection and decoding receiver. Extrinsic information transfer (EXIT) charts are used to obtain the edge degree distribution of the irregular LDPC code which is optimized for the input-output transfer chart of the MMSE-SIC detector. It is shown that the performance of the designed LDPC code is much better than that of conventional LDPC code optimized for the AWGN channel.

• ETRI Journal
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• 제45권3호
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• pp.404-417
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• 2023

This paper proposed a novel method for constructing quasi-cyclic low-density parity-check (QC-LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC-LDPC codes. Investigations revealed that the proposed large-sized QC-LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10^-10 at 3.5 dB E_b/N₀ than conventional LDPC codes, which showed a BER of 10^-7 at 3 dB E_b/N₀. Subsequently, implementation of the proposed QC-LDPC code in a softwaredefined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10^-6 at 4.2 dB E_b/N₀ was achieved. Then, the performance of the proposed codes based on their encoding-decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed-Solomon codes.

• ETRI Journal
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• 제32권4호
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• pp.603-606
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• 2010

In this letter, we propose a channel estimation algorithm based on incremental pilots. These are pilots additionally inserted after puncturing the modulated orthogonal frequency division multiplexing (OFDM) symbols to enhance channel estimation performance without lowering bandwidth efficiency. A low-density parity-check code puncturing scheme is also proposed to prevent the performance degradation due to the codeword bit loss caused by punctured OFDM symbols.

• Journal of Communications and Networks
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• 제17권4호
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• pp.346-350
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• 2015

It is known that the progressive edge-growth (PEG) algorithm can be used to construct low-density parity-check (LDPC) codes at finite code lengths with large girths through the establishment of edges between variable and check nodes in an edge-by-edge manner. In [1], the authors derived a class of LDPC codes for relay communication systems by extending the full-diversity root-LDPC code. However, the submatrices of the parity-check matrix H corresponding to this code were constructed separately; thus, the girth of H was not optimized. To solve this problem, this paper proposes a modified PEG algorithm for use in the design of large girth and full-diversity LDPC codes. Simulation results indicated that the LDPC codes constructed using the modified PEG algorithm exhibited a more favorable frame error rate performance than did codes proposed in [1] over block-fading channels.