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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Fully parallel low-density parity-check code-based polar decoder architecture for 5G wireless communications

  • Dinesh Kumar Devadoss (Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College) ;
  • Shantha Selvakumari Ramapackiam (Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College)
  • Received : 2023.01.06
  • Accepted : 2023.06.07
  • Published : 2024.06.20
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Abstract

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10-4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

Keywords

Acknowledgement

The authors would like to thank SERB, DST for their financial support toward the procurement of EDA tools and hardware for this research under the TARE scheme (grant number: TAR/2020/000001). The authors also thank Dr. Radhakrishna Ganti, Electrical Engineering IITM for providing access to the 5G Lab and extending the necessary facilities.

References

  1. 3GPP, Technical specification group radio access network; nr; multiplexing and channel coding (release 15).
  2. E. Arikan, Channel polarization: a method for constructing capacity-achieving codes for symmetric binary-input memoryless channels, IEEE Trans. Inf. Theory 55 (2009), no. 7, 3051-3073.
  3. A. Eslami and H. Pishro-Nik, A practical approach to polar codes, (IEEE International Symposium on Information Theory Proceedings, Phoenix, AZ, USA), 2011, pp. 16-20.
  4. N. Goela, S. B. Korada, and M. Gastpar, On LP decoding of polar codes, (IEEE Information Theory Workshop, Dublin, Ireland), 2010, pp. 1-5.
  5. N. Hussami, S. B. Korada, and R. Urbanke, Performance of polar codes for channel and source coding, (IEEE International Symposium on Information Theory, Seoul, Rep. of Korea), 2009, pp. 1488-1492.
  6. G. Berhault, C. Leroux, C. Jego, and D. Dallet, Partial sums generation architecture for successive cancellation decoding of polar codes, (Signal Progessing Systems 2013 IEEE workshop on, Taipei, Taiwan), 2013 Proceedings, 2013, pp. 407-412.
  7. C. Leroux, A. J. Raymond, G. Sarkis, and W. J. Gross, A semi-parallel successive-cancellation decoder for polar codes, IEEE Trans. Sig. Process. 61 (2013), no. 2, 289-299.
  8. C. Leroux, I. Tal, A. Vardy, and W. J. Gross, Hardware architectures for successive cancellation decoding of polar codes, (IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Prague, Czech Republic), 2011, pp. 1665-1668.
  9. A. J. Raymond and W. J. Gross, A scalable successive-cancellation decoder for polar codes, IEEE Trans. Sig. Process. 62 (2014), no. 20, 5339-5347.
  10. B. Yuan and K. K. Parhi, Low-latency successive-cancellation polar decoder architectures using 2-bit decoding, IEEE Trans. Circ. Syst. I: Reg. Pap. 61 (2014), no. 4, 1241-1254.
  11. C. Zhang, B. Yuan, and K. K. Parhi, Reduced-latency SC polar decoder architectures, (IEEE International Conference on Communications (ICC), Orrawa, Can) 2012, pp. 3471-3475.
  12. I. Tal and A. Vardy, List decoding of polar codes, (2011 IEEE International Symposium on Information Theory Proceedings, St. Petersburg, Russia), 2011, pp. 1-5.
  13. B. Yuan and K. K. Parhi, Successive cancellation list polar decoder using log-likelihood ratios, (48th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA), 2014, pp. 548-552.
  14. B. Yuan and K. K. Parhi, Low-latency successive-cancellation list decoders for polar codes with multibit decision, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23 (2015), no. 10, 2268-2280.
  15. O. Dizdar and E. Arkan, A high-throughput energy-efficient implementation of successive cancellation decoder for polar codes using combinational logic, IEEE Trans. Circ. Syst. I: Reg. Pap. 63 (2016), no. 3, 436-447.
  16. F. Ercan, C. Condo, and W. J. Gross, Reduced-memory high-throughput fast-SSC polar code decoder architecture, (IEEE International Workshop on Signal Processing Systems (SIPS), Lorient, France), 2017, pp. 1-6.
  17. P. Giard, G. Sarkis, C. Thibeault, and W. J. Gross, 237 Gbit/s unrolled hardware polar decoder, Electron. Lett. 51 (2015), no. 10, 762-763.
  18. P. Giard, G. Sarkis, C. Thibeault, and W. J. Gross, A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs, (IEEE Workshop on Signal Processing Systems (SIPS), Hangzhou, China), 2015, pp. 1-6.
  19. X. Zhang, X. Yan, Q. Zeng, J. Cui, N. Cao, and R. Higgs, High-throughput fast-SSC polar decoder for wireless communications, Wireless Commun. Mob. Comput. 51 (2018), 1-10.
  20. A. Pamuk, An FPGA implementation architecture for decoding of polar codes, (8th International Symposium on Wireless Communication Systems, Aachen, Germany), 2011, pp. 437-441.
  21. B. Yuan and K. K. Parhi, Architecture optimizations for BP polar decoders, (IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada), 2013, pp. 2654-2658.
  22. B. Yuan and K. K. Parhi, Architectures for polar BP decoders using folding, (IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia), 2014, pp. 205-208.
  23. B. Yuan and K. K. Parhi, Early stopping criteria for energy-efficient low-latency belief-propagation polar code decoders, IEEE Trans. Sig. Process. 62 (2014), no. 24, 6496-6506.
  24. S. M. Abbas, Y. Fan, J. Chen, and C.-Y. Tsui, Low complexity belief propagation polar code decoder, (IEEE Workshop on Signal Processing Systems (SIPS), Hangzhou, China), 2015, pp. 1-6.
  25. S. Cammerer, M. Ebada, A. Elkelesh, and S. Ten Brink, Sparse graphs for belief propagation decoding of polar codes, (IEEE International Symposium on Information Theory (ISIT), Vail, CO, USA), 2018, pp. 1465-1469.
  26. W. Qiao, D. Liu, and S. Liu, QFEC ASIP: a flexible quad-mode FEC ASIP for polar, LDPC, turbo, and convolutional code decoding, IEEE Access 6 (2018), 72189-72200.
  27. Y. Wang, H. Yu, and W. Wang, A general decoder architecture for LDPC and polar codes on sparse bipartite graphs, (IEEE 5th International Conference on Computer and Communications (ICCC), Chengdu, China), 2019, pp. 1585-1591.
  28. D. Dinesh Kumar and R. Shantha Selvakumari, Semiparallel polar decoder architecture using shift-register-based partial-sum computation for 5G mobile communications, Mater. Today: Proc. 62 (2022), 4985-4990. International Conference on Innovative Technology for Sustainable Development.
  29. D. Dinesh Kumar and R. Shantha Selvakumari, Improving utilization rate of semi-parallel successive cancellation architecture for polar codes using 2-bit decoding, Turkish J. Electr. Eng. Comput. Sci. 30 (2022), no. 3, 713-729.
  30. V. Bioglio, C. Condo, and I. Land, Design of polar codes in 5G new radio, IEEE Commun. Surv. Tutor. 23 (2021), no. 1, 29-40.
  31. T. R. Halford and K. M. Chugg, An algorithm for counting short cycles in bipartite graphs, IEEE Trans. Inf. Theory 52 (2006), no. 1, 287-292.
  32. C. Xiong, Y. Zhong, C. Zhang, and Z. Yan, An FPGA emulation platform for polar codes, (IEEE International Workshop on Signal Processing Systems (SIPS), Dallas, TX, USA), 2016, pp. 148-153.
  33. C. Xia, Y. Fan, J. Chen, C. Tsui, C. Zeng, J. Jin, and B. Li, An implementation of list successive cancellation decoder with large list size for polar codes, (27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium), 2017, pp. 1-4.
  34. D. Dinesh Kumar and R. Shantha Selvakumari, Performance analysis of min-sum based LDPC decoder architecture for 5g new radio standards, Mater. Today: Proc. 62 (2022), 4965- 4972. International Conference on Innovative Technology for Sustainable Development.
  35. V. L. Petrovi, M. M. Markovi, D. M. E. Mezeni, L. V. Saranovac, and A. Radoevi, Flexible high throughput QC-LDPC decoder with perfect pipeline conflicts resolution and efficient hardware utilization, IEEE Trans. Circ. Syst. I: Reg. Pap. 67 (2020), no. 12, 5454-5467.