• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.10
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• pp.912-917
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• 2006

In this paper, Trench emitter electrode IGBT structure is proposed and studied numerically using the device simulator, MEDICI. The breakdown voltage, on-state voltage drop, latch up current density and turn-off time of the proposed structure are compared with those of the conventional trench gate IGBT(TIGBT) structures. Enhancement of the breakdown voltage by 19 % is obtained in the proposed structure due to dispersion of electric field at the edge of the bottom trench gate by trench emitter electrode. In addition, the on-state voltage drop and the latch up current density are improved by 25 %, 16 % respectively. However increase of turn-off time in proposed structures are negligible.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.632-634
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• 2004

First for high-qualify images and reducing process-error and driving speed, the designed 8-bit data driving circuit consists of a constant transconductance bias circuit, D-F/Fs by shift registers using static transmission gates, 1st latch and 2nd latch by tristate inverters, level shifters, current steering segmented D/A converters by 4MSB thermometer decoder and 4LSB weighted type. Second, we designed gray amp for power saving. These data driving circuits are designed with $0.35-{\mu}m$ CMOS technologies at 3.3 V and 18 V power supplies and simulated with HSPICE.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.10
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• pp.75-79
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• 2013

The automatic quiescent power cut-off receptacles(QPCR from now on) have achieved a noticeable energy saving so far. The government is preparing a new code for wider promotion of the QPCRs. This paper presents a new QPCR that adopts the latch relay instead of the conventional coil-operated relay. Measurement results of the prototype have shown up to 0.22W improvement of quiescent power compared with existing products.

• ETRI Journal
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• v.25 no.5
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• pp.321-327
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• 2003

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1283-1286
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• 2006

A holding latch with level shifting function is proposed for power and cost effectiveness with low temperature polycrystalline silicon technology on the glass backplane. Layout area and power consumption of the proposed circuit are reduced by 10% and 52% compared with those of the typical structure which combines a static D-latch and a cross coupled level shifter for 2.2" qVGA panel, respectively.

• Transactions on Electrical and Electronic Materials
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• v.8 no.1
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• pp.21-25
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• 2007

A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.160-163
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• 2000

In this paper, we propose an efficient technique to minimize the input offset of a dynamic latch comparator. We analyzed offset due to charge injection mismatching and unwanted positive feedback during sampling phase. The last one was only considered in the previous works. Based on the analysis, we proposed a modified dynamic latch with initialization switch. The proposed circuit was simulated using 0.65$\mu\textrm{m}$ CMOS process parameter with 5v supply. The simulation results showed that the input offset is less than 5mv at 200㎒ sampling frequency and the input offset is improved about 80% compared with previous work in 5k$\Omega$ input resistance.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.9
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• pp.1764-1771
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• 2002

The latch needle cam system of circular knitting machines is analysed using multibody dynamics. A formulation is made to obtain the vertical stiffness between the needle and the cam. By implementing this formulation into the data of the multibody dynamics program, the motion of the needle is described and the forces and impulses between the needle and the cam are obtained.

• Special Issue of the Society of Naval Architects of Korea
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• 2013.12a
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• pp.60-65
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• 2013

Now days, the demands of new type hull lines and optimum design in relation with the EEDI (Energy Efficiency Design Index) regulation and eco-friendly high efficiency vessel design are mandatory clauses in Euro financial crises era. Therefore, in correlation with the above, we tried to find the optimum results and revealed the alterations of supporting structure for liftable car deck latch on PCTC. Generally, PCTC (Pure Car & Truck Carrier) design has been performed by 2 pillar space model F. E analysis without vehicle loads on liftable car deck to evaluate the structural adaptability. So, we applied mentioned vehicle loads on pillar and side transverse web on model to compare with not applied model and performed the ultimate strength analysis of improved design for the safety evaluation.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.63-66
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• 2005

A soft error rate neutrons is a growing problem for integrated circuits with technology scaling. In the acceleration test with high-density neutron beam, a latch-up prohibits accurate estimations of the soft error rate (SER). This paper presents results of analysis for the latch-up characteristics in the circumstance corresponding to the acceleration SER test for SRAM. Simulation results, using a two-dimensional device simulator, show that the deep p-well structure has better latch-up Immunity compared to normal twin and triple well structures. In addition, it is more effective to minimize the distance to ground power compared with controlling a path to the $V_{DD}$ power.