• Title/Summary/Keyword: Latch

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Child Occupant Safety According to the ISOFIX Type of CRS (CRS의 부착방식에 따른 어린이 탑승자 안전도 비교)

  • 이재완;윤영한;박경진
    • Transactions of the Korean Society of Automotive Engineers
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    • v.11 no.4
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    • pp.86-93
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    • 2003
  • These days, automobile industry pays considerable attention to child occupant safety. As the US adopted requirements for universal and uniform anchor systems for child restraints, manufacturers for child seats put an enormous effort to improve the protective properties of Child Restraint System (CRS). Various standards have been studied and announced by different countries. The anchorage system is the most important in the CRS and the rules of universal anchor are to provide devices which are independent of safety belts. A new concept called International Standard Organization Fixture (ISOFIX) has been announced. It suggests some designs for the CRS. In this study, the suggested designs are evaluated with domestic products. Tests are performed and the results are incorporated into a finite element modeling process. As the finite element model is established, various numerical tests are conducted and the numerical results are discussed. A commercial software system is utilized for the nonlinear finite element analysis.

Development Pole Transformer with Automatic Tap Changer (자동 탭 절환 내장형 주상변압기 개발에 관한 연구)

  • Nam-Koong, Won;Lee, Sung-Woo;Jang, Moon-Jong
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.27 no.9
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    • pp.108-113
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    • 2013
  • Change of supply voltage, customer load, output of distributed generation, etc cause voltage change in distribution system. OLTC and SVR are usually used to supply normal voltage at customer. But usage of these devices is inefficient and uneconomical in certain circumstances. To solve this problem, new pole transformer which has automatic tap changer is developed. The transformer changes tap when voltage changes. And it has latch switch and reactor for supplying power without outage. To verify normal operation of tap changer, test is conducted. SVR and 50kVA load is used for test.

The DWA Design with Improved Structure by Clock Timing Control (클록 타이밍 조정에 의한 개선된 구조를 가지는 DWA 설계)

  • Kim, Dong-Gyun;Shin, Hong-Gyu;Cho, Seong-Ik
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.59 no.4
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    • pp.401-404
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    • 2010
  • In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

A new structure of completely isolated MOSFET using trench method with SOI (SOI기판과 트렌치 기법을 이용한 완전 절연된 MOSFET의 전기적인 특성에 관한 연구)

  • Park, Yun-Sik;Kang, Ey-Goo;Kim, Sang-Sig;Sung, Man-Young
    • Proceedings of the KIEE Conference
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    • 2002.11a
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    • pp.159-160
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    • 2002
  • 본 논문에서는 반도체 응용부문 중 그 활용도가 높은 MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)의 새로운 구조를 제안하였다. 제안한 소자를 가지고 전자회로의 구성할 때 인접 디바이스들과 연계되어 발생되는 래치 업(latch-up)을 근본적으로 제거하고, 개별소자의 완전한 절연을 실현하였으며 누설전류 또한 제거된다. 이는 SOI기판 위에 벌크실리콘 공정을 이용하여 구현된다. 즉, 소자 양옆의 트랜치 웰(Trench-well)과 SOI 기판의 절연층으로 소자의 독립성을 지켜준다. 또한 게이트 절연층을 트랜치 구조로 기존 MOS구조의 채널 부분에 위치시키고 드레인과 소스를 위치시켜 자연적으로 자기정렬이 되어진다. 이와 같은 과정으로 게이트-소스, 게이트-드레인 기생 커패시터의 효과를 현저히 줄일 수 있다.

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The thermal conductivity analysis of the SOI LIGBT structure using $Al_2O_3$ ($Si/Al_2O_3/Si$ 형태의 SOI(SOS) LIGBT 구조에서의 열전도 특성 분석)

  • Kim, Je-Yoon;Kim, Jae-Wook;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.11a
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    • pp.163-166
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    • 2003
  • The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2\;and\;Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability

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A Study on the Design of a ROIC for Uncooled Bolometer Thermal Image Sensor using Reference Resistor Compensation (기준저항 보상회로를 이용한 비냉각형 볼로미터 검출회로의 설계에 관한 연구)

  • Yu, Seung-Woo;Kwak, Sang-Hyeon;Jung, Eun-Sik;Sung, Man-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.2
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    • pp.119-122
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    • 2009
  • As infrared light radiates, the CMOS Readout IC (ROIC) for the microbolometer typed infrared sensor detects voltage or current which is caused by the variation of resistance in the bolometer sensor. A serious problem we may have in designing the ROIC is the value of bolometer and reference resistors will be changed due to process variation. Since each pixel does not have the same value of resistance, fixed pattern noise problems happen during the sensor operations. In this paper, we propose a novel technique to compensate the fluctuation of reference resistance with taking account of process variation. By using a comparator and a cross coupled latch, we will make the value of reference resistor same as the bolometer's.

5-T and 6-T thermometer-code latches for thermometer-code shift-register

  • Woo, Ki-Chan;Yang, Byung-Do
    • ETRI Journal
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    • v.43 no.5
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    • pp.900-908
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    • 2021
  • This paper proposes thermometer-code latches having five and six transistors for unidirectional and bidirectional thermometer-code shift-registers, respectively. The proposed latches omit the set and reset transistors by changing from two supply voltage nodes to the set and reset signals in the cross-coupled inverter. They set or reset the data by changing the supply voltage to ground in either of two inverters. They reduce the number of transistors to five and six compared with the conventional thermometer-code latches having six and eight transistors, respectively. The proposed thermometer-code latches were simulated using a 65 nm complementary metal-oxide-semiconductor (CMOS) process. For comparison, the proposed and conventional latches are adapted to the 64 bit thermometer-code shift-registers. The proposed unidirectional and bidirectional shift-registers occupy 140 ㎛2 and 197 ㎛2, respectively. Their consumption powers are 4.6 ㎼ and 5.3 ㎼ at a 100 MHz clock frequency with the supply voltage of 1.2 V. They decrease the areas by 16% and 13% compared with the conventional thermometer-code shift-register.

Dimming Control of LED Light Using Pulse Frequency Modulation in Visible Light Communication

  • Lee, Seong-Ho
    • Journal of information and communication convergence engineering
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    • v.19 no.4
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    • pp.269-275
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    • 2021
  • Light-emitting diodes (LEDs) are modulated using a square wave pulse sequence for flicker prevention and dimming control in visible light communication (VLC). In a VLC transmitter, the high and low bits of the non-return-to-zero (NRZ) data are converted to two square waves of different frequencies, which continue for a finite time defined by the fill ratio in an NRZ bit time. As the average optical power was kept constant and independent of data transmission, the LED was flicker-free. Dimming control is carried out by changing the fill ratio of the square wave in the NRZ bit time. In the experiments, the illumination of the LED light was controlled in the range of approximately 19.2% to 96.2% of the continuous square wave modulated LED light. In the VLC receiver, a high-pass filter combined with a latch circuit was used to recover the transmitted signal while preventing noise interference from adjacent lighting lamps.

A Research on Dynamic Behavior of Clamshell Hood to Secure the Safety and Durability Performance

  • Kyoungtaek Kwak;Seunghoon Kang;Jaedong Yoo;Kyungdug Seo;Youngchul Shin;Kyungsup Chun;Jaekyu Lee
    • Journal of Auto-vehicle Safety Association
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    • v.15 no.1
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    • pp.7-15
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    • 2023
  • The purpose of this study is to predict the dynamic behavior of clamshell hood system on the harsh road driving condition, and secure the safety and durability performance of the system. The equation of motion of hood system is derived and the numerical analysis is implemented to obtain the lateral movement of the hood system. Also, the actual Belgian road test results are correlated to the predicted ones, and confirm the reliability of the system. Then, the parameter study is conducted to figure out the sensitive factors to affect the dynamic behavior, and the engineering design guide to make the system robust to confine the minimum friction force generated from hood latch and maximum hood weight is suggested from this research.

Design and Implementation of a Concuuuency Control Manager for Main Memory Databases (주기억장치 데이터베이스를 위한 동시성 제어 관리자의 설계 및 구현)

  • Kim, Sang-Wook;Jang, Yeon-Jeong;Kim, Yun-Ho;Kim, Jin-Ho;Lee, Seung-Sun;Choi, Wan
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.4B
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    • pp.646-680
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    • 2000
  • In this paper, we discuss the design and implementation of a concurrency control manager for a main memory DBMS(MMDBMS). Since an MMDBMS, unlike a disk-based DBMS, performs all of data update or retrieval operations by accessing main memory only, the portion of the cost for concurrency control in the total cost for a data update or retrieval is fairly high. Thus, the development of an efficient concurrency control manager highly accelerates the performance of the entire system. Our concurrency control manager employs the 2-phase locking protocol, and has the following characteristics. First, it adapts the partition, an allocation unit of main memory, as a locking granule, and thus, effectively adjusts the trade-off between the system concurrency and locking cost through the analysis of applications. Second, it enjoys low locking costs by maintaining the lock information directly in the partition itself. Third, it provides the latch as a mechanism for physical consistency of system data. Our latch supports both of the shared and exclusive modes, and maximizes the CPU utilization by combining the Bakery algorithm and Unix semaphore facility. Fourth, for solving the deadlock problem, it periodically examines whether a system is in a deadlock state using lock waiting information. In addition, we discuss various issues arising in development such as mutual exclusion of a transaction table, mutual exclusion of indexes and system catalogs, and realtime application supports.

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