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5-T and 6-T thermometer-code latches for thermometer-code shift-register

  • Woo, Ki-Chan (Department of Electronics Engineering, Chungbuk National University) ;
  • Yang, Byung-Do (Department of Electronics Engineering, Chungbuk National University)
  • Received : 2020.08.21
  • Accepted : 2020.12.21
  • Published : 2021.10.01

Abstract

This paper proposes thermometer-code latches having five and six transistors for unidirectional and bidirectional thermometer-code shift-registers, respectively. The proposed latches omit the set and reset transistors by changing from two supply voltage nodes to the set and reset signals in the cross-coupled inverter. They set or reset the data by changing the supply voltage to ground in either of two inverters. They reduce the number of transistors to five and six compared with the conventional thermometer-code latches having six and eight transistors, respectively. The proposed thermometer-code latches were simulated using a 65 nm complementary metal-oxide-semiconductor (CMOS) process. For comparison, the proposed and conventional latches are adapted to the 64 bit thermometer-code shift-registers. The proposed unidirectional and bidirectional shift-registers occupy 140 ㎛2 and 197 ㎛2, respectively. Their consumption powers are 4.6 ㎼ and 5.3 ㎼ at a 100 MHz clock frequency with the supply voltage of 1.2 V. They decrease the areas by 16% and 13% compared with the conventional thermometer-code shift-register.

Keywords

Acknowledgement

The chip fabrication and EDA tool were supported by the IC Design Education Center (IDEC), South Korea.

References

  1. C.-C. Liu et al., A 10 bit 50 MS/s SAR ADC with a monotonic capacitor switching procedure, IEEE J. Solid-State Circuits 45 ( 2010 ), no. 4, 731-740. https://doi.org/10.1109/JSSC.2010.2042254
  2. X. Zhang et al., A 0.6 V input CCM/DCM operating digital buck converter in 40 nm CMOS, IEEE J. Solid-State Circuits 49 ( 2014 ), no. 11, 2377-2386. https://doi.org/10.1109/JSSC.2014.2339325
  3. M. Huang et al., A fully integrated digital LDO with coarse-fine-tuning and burst-mode operation, IEEE Trans. Circuits Syst. II: Express Briefs 63 ( 2016 ), no. 7, 683-687. https://doi.org/10.1109/TCSII.2016.2530094
  4. B.-D. Yang, Low-power and area-efficient shift register using pulsed latches, IEEE Trans. Circuits Syst. I: Regul. Pap. 62 ( 2015 ), no. 6, 1564-1571. https://doi.org/10.1109/TCSI.2015.2418837
  5. K. Woo, H. Kang, and B. Yang, Area-efficient bidirectional shift-register using bidirectional pulsed-latches, IEEE Trans. Circuits Syst. II: Express Briefs 66 ( 2019 ), no. 8, 1386-1390. https://doi.org/10.1109/tcsii.2018.2882810
  6. K. Woo, H. Kang, and B. Yang, Low-area and low-power latch-based thermometer-code shift-register, IEEE Trans. Circuits Syst. II: Express Briefs 67 ( 2019 ), no. 10, 2119-2123. https://doi.org/10.1109/tcsii.2019.2943004
  7. H. Jeong et al., Self-timed pulsed latch for low-voltage operation with reduced hold time, IEEE J. Solid-State Circuits 54 ( 2019 ), no. 8, 2304-2315. https://doi.org/10.1109/jssc.2019.2907774
  8. N. Kawai et al., A fully static topologically-compressed 21-transistor flip-flop with 75% power saving, IEEE J. Solid-State Circuits 49 ( 2014 ), no. 11, 2526-2533. https://doi.org/10.1109/JSSC.2014.2332532
  9. J.-F. Lin et al., Low-power 19-transistor true single-phase clocking flip-flop design based on logic structure reduction schemes, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 ( 2017 ), no. 11, 3033-3044. https://doi.org/10.1109/TVLSI.2017.2729884