• 한국전기전자재료학회논문지
• /
• 제14권11호
• /
• pp.912-916
• /
• 2001

Fluxmeter is a measuring instrument the magnetic flux intensity by means of an integration of the voltage induced to a search coil to unit time. It also is required to a precise integrator since the voltage induced to a search coil has a differential value of the flux ${\Phi}$ to unit time. In this study, a bias current which is a main problem of the integrator in a drift troublesome depending on the temperature of a FET is investigated. We have confirmed that the temperature dependence of both the bias current of a integrator using the FET and the reversal saturated current of the minor carrier in a P-N junction of a semiconductor were the same. The property of a commercial integrator goes rapidly down with increasing temperature. The bias current of a FET is increased twice as much with 10$^{\circ}C$ increment. As a result, the low drift integrator could be developed by setting the lower temperature up with a pottier device.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
• /
• pp.385-388
• /
• 2000

In this paper, the Ka-band Dielectric resonator oscillator has been designed and fabricated. The resonator network was simulated using HFSS program. The design method of an oscillator is the small-signal S-parameter design. The Push-push DRO employs a hetero junction FET (NE32484A). The fabricated Push-push DRO shows such characteristics as the phase noise -106 ㏈c/Hz at the 100 ㎑ frequency offset. the output power and fundamental frequency surpression were -6 ㏈m and -29 ㏈c, respectively.

• Journal of Power Electronics
• /
• 제11권2호
• /
• pp.188-193
• /
• 2011

A highly efficient AC-DC converter for small wind power generation systems using a brushless DC generator (BLDCG) is presented in this paper. The market standard AC-DC converter for a BLDCG consists of a three-phase diode rectifier and a boost DC-DC converter, which has an IGBT and a fast recovery diode (FRD). This kind of two-stage solution basically suffers from a large amount of conduction loss and the efficiency greatly decreases under a light load, or at a low current, because of the switching devices with a P-N junction. In order to overcome this low efficiency, especially at a low current, a three-phase bridgcless converter consisting of three upper side FRDs and three lower side Super Junction FETs is presented. In the overall operating speed region, including the cut-in speed, the efficiency of the proposed converter is improved by up to 99%. Such a remarkable result is validated and compared with conventional solutions by calculating the power loss based on I-V curves and the switching loss data of the adopted commercial switches and the current waveforms obtained through PSIM simulations.

• 한국ITS학회 논문지
• /
• 제2권2호
• /
• pp.65-72
• /
• 2003

본 연구를 통하여 MMC(Microwave Micro Cell)를 위한 무선 중계 시스템과 ITS용 무선장비등에 사용 될 수있는 6단의 하이브리드 전력증폭기를 설계 및 제작하였다. 전력 증폭기 각단의 능동소자는 bare chip 형태의 Hetero-junction Power FET를 이용하였으며, $\varepsilon_{r}$=9.9, 15-mil 두께의 알루미나기판을 사용하여 제작하였다. 측정 결과 시스템의 순방향 주파수인 17.6GHz - 17.gGEU에서 33.2~36.5dB의 소신호 이득과 33.0$\~$34.0dBm까지의 출력전력을 얻었고, 역방향 주파수인 19.0GHt$\~$19.2GHz에서 36.0$\~$37.0dB의 소신호 이득을 출력전력은 33.0$\~$34.5dBm을 얻었다.

• 한국방송∙미디어공학회:학술대회논문집
• /
• 한국방송공학회 1996년도 학술대회
• /
• pp.27-31
• /
• 1996

In this paper, The SSPA(Solid State Power Amplifier) is 100 watts amplifier which is used with C-Band Satellite communication Up-Link frequency, 5.875 ∼6.425 GHz. SSPA requires more output power than is available from a single GaAs FET with result it is necessary to combine the output of many device. To achieve a high power, it is important to make a good N-way power divider which has a small different phase, good combining efficiency and high power handling capability. The reliability of Power GaAs FET decrease with increasing junction temperature, power amplifier in general dissipate amount of power. It is important to provide them with a heatsink and a temperature compensation circuit to dispose of the unwanted heat. To compensate temperature, Using PIN diode attenuator, it is enable to get a precision gain control. The output power of the SSPA is more than 100 watt with which the TWTA (Traveling-Wave Tube Amplifier) can be replaced. Each stage was measured by the Network analyzer PH8510C, Power meter Booton 42BD, The gain is more than 53 dB, flatness is less than 1.5 dB.

• 한국전기전자재료학회논문지
• /
• 제36권4호
• /
• pp.413-417
• /
• 2023

Gallium Oxide (Ga₂O₃) is preferred as a material for next generation power semiconductors. The Ga₂O₃ should solve the disadvantages of low thermal resistance characteristics and difficulty in forming an inversion layer through p-type ion implantation. However, Ga₂O₃ is difficult to inject p-type ions, so it is being studied in a heterojunction structure using p-type oxides, such as NiO, SnO, and Cu₂O. Research the lateral-type FET structure of NiO/Ga₂O₃ heterojunction under the Gate contact using the Sentaurus TCAD simulation. At this time, the VG-ID and VD-ID curves were identified by the thickness of the Epi-region (channel) and the doping concentration of NiO of 1×10¹⁷ to 1×10¹⁹ cm-3. The increase in Epi region thickness has a lower threshold voltage from -4.4 V to -9.3 V at I_D = 1×10^-8 mA/mm, as current does not flow only when the depletion of the PN junction extends to the Epi/Sub interface. As an increase of NiO doping concentration, increases the depletion area in Ga₂O₃ region and a high electric field distribution on PN junction, and thus the breakdown voltage increases from 512 V to 636 V at I_D =1×10^-3 A/mm.

• 한국진공학회지
• /
• 제17권3호
• /
• pp.199-203
• /
• 2008

$O_2$ 플라즈마를 이용한 표면처리 공정이 Bio-FET (biologically sensitive field-effect transistor)에 미치는 영향을 조사하기 위하여, SOI (Silicon-on-Insulator) wafer와 sSOI (strained- Si-on-Insulator) wafer를 이용하여 pseudo-MOSFET을 제작하고 $O_2$ 플라즈마를 이용하여 표면처리를 진행하였다. 제작된 시료들은 back gated metal contact junction 방식으로 측정되었다. $I_D-V_G$ 특성과 field effect mobility 특성의 관찰을 통하여 $O_2$ 플라즈마 표면처리에 따른 각 시료들의 전기적 특성 변화에 대하여 관찰하였다. 그리고 $O_2$ 플라즈마 표면처리 과정에서 플라즈마에 의한 손상을 받은 시료들은 2% 수소희석가스 ($H_2/N_2$)를 이용한 후속 열처리 공정을 진행한 후 전기적 특성이 향상되는 것을 관찰할 수 있었다. 이는 수소희석가스를 이용한 후속 열처리 공정을 통하여 산화막과 Si 사이의 계면 준위와 산화막 내부의 전하 포획 준위를 감소시켰기 때문이다.

• 한국전기전자재료학회논문지
• /
• 제28권11호
• /
• pp.683-689
• /
• 2015

For the formation of $N^+$ doping, the antimony ions are mainly used for the fabrication of a BJT (bipolar junction transistor), CMOS (complementary metal oxide semiconductor), FET (field effect transistor) and BiCMOS (bipolar and complementary metal oxide semiconductor) process integration. Antimony is a heavy element and has relatively a low diffusion coefficient in silicon. Therefore, antimony is preferred as a candidate of ultra shallow junction for n type doping instead of arsenic implantation. Three-dimensional (3D) profiles of antimony are also compared one another from different tilt angles and incident energies under same dimensional conditions. The diffusion effect of antimony showed ORD (oxygen retarded diffusion) after thermal oxidation process. The interfacial effect of a $SiO_2/Si$ is influenced antimony diffusion and showed segregation effects during the oxidation process. The surface sputtering effect of antimony must be considered due to its heavy mass in the case of low energy and high dose conditions. The range of antimony implanted in amorphous and crystalline silicon are compared each other and its data and profiles also showed and explained after thermal annealing under inert $N_2$ gas and dry oxidation.

• 대한전자공학회논문지SD
• /
• 제43권11호
• /
• pp.1-7
• /
• 2006

이상적인(ideal) 이중-게이트(double-gate) 벌크(bulk) FinFET의 3차원(3-D) 시뮬레이션을 수행하여 전기적 특성들을 분석하였다. 3차원 시뮬레이터를 이용하여, 게이트 길이($L_g$)와 높이($H_g$), 핀 바디(fin body)의 도핑농도($N_b$)를 변화시키면서 소스/드레인 접합 깊이($X_{jSDE}$)에 따른 문턱전압($V_{th}$), 문턱전압 변화량(${\Delta}V_{th}$), DIBL(drain induced barrier lowering), SS(subthreshold swing)의 특성들을 살펴보았다. 게이트 높이가 35 nm인 소자에서 소스/드레인 접합 깊이(25 nm, 35 nm, 45 nm) 변화에 따라, 각각의 문턱전압을 기준으로 게이트 높이가 $30nm{\sim}45nm$로 변화 될 때, 문턱전압변화량은 20 mV 이하로 그 변화량이 매우 적음을 알 수 있었다. 낮은 핀 바디 도핑농도($1{\times}10^{16}cm^{-3}{\sim}1{\times}10^{17}cm^{-3}$)에서, 소스/드레인 접합 깊이가 게이트전극보다 깊어질수록 DIBL과 SS는 급격히 나빠지는 것을 볼 수 있었고. 이러한 특성저하들은 $H_g$ 아래의 ${\sim}10nm$ 위치에 국소(local) 도핑을 함으로써 개선시킬 수 있었다. 또한 local 도핑으로 소스/드레인 접합 깊이가 얕아질수록 문턱전압이 떨어지는 것을 개선시킬 수 있었다.

• 한국광학회:학술대회논문집
• /
• 한국광학회 1991년도 제6회 파동 및 레이저 학술발표회 Prodeedings of 6th Conference on Waves and Lasers
• /
• pp.190-193
• /
• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.