• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1295-1297
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• 1993

Properties of oxynitride films oxidized by $N_2O$ gas after thermal oxidation and $N_2O$ oxide films directly oxidized using $N_2O$ gas on the bare silicon wafer have been studied. Through the AES analysis, Nitrogen pile-up at the interface of Si/oxynitride and Si/$N_2O$ oxide has observed. Also, it could be presumed that there are differences in the mechanism of the growth of film by observing film growth. $N_2O$ oxide and oxynitride films have the self-limited characteristics. Therefore, it will be possible to obtain ultra-thin films. Nitrogen pile-up at the interfaces Si/oxynitride and Si/$N_2O$ oxide strengthens film structure and improves dielectric reliability. Although fixed charge densities and interface trap densities of $N_2O$ oxide and oxynitride films has somewhat higher than those of thermal $SiO_2,\;N_2O$ oxide and oxynitride films showed improved I-V characteristics and constant current stress.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.473-479
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• 2011

In this paper, we have compared amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) with the nano-crystalline embedded-IGZO ($N_c$-embedded-IGZO) TFT fabricated by solid-phase crystallization (SPC) technique. The field effect mobility (${\mu}_{FE}$) of $N_c$-embedded-IGZO TFT was 2.37 $cm^2/Vs$ and the subthreshold slope (S-factor) was 0.83 V/decade, which showed lower performance than those of a-IGZO TFT (${\mu}_{FE}$ of a-IGZO was 9.67 $cm^2/Vs$ and S-factor was 0.19 V/decade). This results originated from generation of oxygen vacancies in oxide semiconductor and interface between gate insulator and semiconductor due to high temperature annealing process. However, the threshold voltage shift (${\Delta}V_{TH}$) of $N_c$-embedded-IGZO TFT was 0.5 V, which showed 1 V less shift than that of a-IGZO TFT under constant current stress during $10^5$ s. This was because there were additionally less increase of interface trap charges in Nc-embedded-IGZO TFT than a-IGZO TFT.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.12
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• pp.2265-2269
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• 2011

1 kV high-voltage GaN Schottky diode is realized using GaN-on-Si template by oxidizing Ni-Schottky contact. The Auger electron spectroscopy (AES) analysis revealed the formation of $NiO_x$ at the top of Schottky contact. The Schottky contact was changed to from Ni/Au to Ni/Ni-Au alloy/Au/$NiO_x$ by oxidation. Ni diffusion into AlGaN improves the Schottky interface and the trap-assisted tunneling current. In addition, the reverse leakage current and the isolation-leakage current are efficiently suppressed by oxidation. The isolation-leakage current was reduced about 3 orders of magnitudes. The reverse leakage current was also decreased from 2.44 A/$cm^2$ to 8.90 mA/$cm^2$ under -100 V-biased condition. The formed group-III oxides ($AlO_x$ and $GaO_x$) during the oxidation is thought to suppress the surface leakage current by passivating surface dangling bonds, N-vacancies and process damages.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.215.2-215.2
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• 2015

We fabricated dual active layer (DAL) thin film transistors (TFTs) with indium tin zinc oxide (ITZO) and indium gallium zinc oxide (IGZO) thin film layers using solution process. The ITZO and IGZO layer were used as the front and back channel, respectively. In order to investigate the bias stress stability of ITZO SAL (single active layer) and ITZO/IGZO DAL TFT, a gate bias stress of 10 V was applied for 1500 s under the dark condition. The SAL TFT composed of ITZO layer shows a poor positive bias stability of ${\delta}VTH$ of 13.7 V, whereas ${\delta}VTH$ of ITZO/IGZO DAL TFT was very small as 2.6 V. In order to find out the evidence of improved bias stress stability, we calculated the total trap density NT near the channel/gate insulator interface. The calculated NT of DAL and SAL TFT were $4.59{\times}10^{11}$ and $2.03{\times}10^{11}cm^{-2}$, respectively. The reason for improved bias stress stability is due to the reduction of defect sites such as pin-hole and pores in the active layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.597-597
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• 2013

The resistive switching behaviors of Pt nanodisk on Nb-doped SrTiO3 single-crystal have been studied with conductive atomic force microscopy in ultra-high vacuum. The nanometer sizes of Pt disks were formed by using self-assembled patterns of silica nanospheres on Nb-doped SrTiO3 single-crystal semiconductor film using the Langmuir-Blodgett, followed by the metal deposition with e-beam evaporation. The conductance images shows the spatial mapping of the current flowing from the TiN coated AFM probe to Pt nanodisk surface on Nb：STO single-crystal substrate, that was simultaneously obtained with topography. The bipolar resistive switching behaviors of Pt nanodisk on Nb：STO single-crystal junctions was observed. By measuring the current-voltage spectroscopy after the forming process, we found that switching behavior depends on the charging and discharging of interface trap state that exhibit the high resistive state (HRS) and low resistive state (LRS), respectively. The results suggest that the bipolar resistive switching of Pt/Nb:STO single-crystal junctions can be performed without the electrochemical redox reaction between tip and sample with the potential application of nanometer scale resistive switching devices.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.1
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• pp.112-116
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• 2007

We have investigated the hysteresis phenomenon of a hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) and analyzed the effect of hysteresis phenomenon when a-Si:H TFT is a pixel element of active matrix organic light emitting diode (AMOLED). When a-Si:H TFT is addressed to different starting gate voltages, such as 10V and 5V, the measured transfer characteristics with 1uA at $V_{DS}$ = 10V shows that the gate voltage shift of 0.15V is occurred due to the different quantities of trapped charge. When the step gate-voltage in the transfer curve is decreased from 0.5V to 0.05V, the gate-voltage shift is decreased from 0.78V to 0.39V due to the change of charge do-trapping rate. The measured OLED current in the widely used 2-TFT pixel show that a gate-voltage of TFT in the previous frame can influence OLED current in the present frame by 35% due to the change of interface trap density induced by different starting gate voltages.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.145-145
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• 2010

It is observed from SEM images that many voids were created after annealed by helium gas. The PL spectra of the ZnO samples revealed the strong violet emission peaks at 3.05 eV with the relative weak near band edge UV emissions. It was concluded from experiment results that native $Zn_i$ and $V_o$ donor defect levels can be generated below the conduction band edge due to the incorporation of helium atoms decomposed from helium gas into the ZnO matrix. He atoms in ZnO matrix will affect the interface trap existing in depletion regions located at the grain boundaries, which leads to the creation of $Zn_i$ and $V_o$ donor defect levels.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.80-81
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• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.158-166
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• 2001

Based on uniform hot carrier injection (optically assisted electron injection) across the $Si-SiO_2$ interface into the gate insulator of n-channel IGFETs, the threshold voltage shifts associated with electron injection of $1.25{\times}l0^{16}{\;}e/\textrm{cm}^2 between 0.5 and 7 MV/cm were found to decrease from positive to negative values, indicating both a decrease in trap cross section ($E_{ox}{\geq}1.5 MV/cm$) and the generation of FPC $E_{ox}{\geq}5{\;}MV/cm$). It was also found that FNC and large cross section NETs were generated for $E_{ox}{\geq}5{\;}MV/cm$. Continuous, uniform low-field (1MV/cm) electron injection up to $l0^{19}{\;}e/\textrm{cm}^2 is accompanied by a monatomic increase in threshold voltage. It was found that the data could be modeled more effectively by assuming that most of the threshold voltage shift could be ascribed to generated bulk defects which are generated and filled, or more likely, generated in a charged state. The injection method and conditions used in terms of injection fluence, injection density, and temperature, can have a dramatic impact on what is measured, and may have important implications on accelerated lifetime measurements.