• 전자공학회논문지A
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• 제28A권12호
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• pp.46-52
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• 1991

A new signal process circuit using two ISFETs as the input devices of the MOS differential amplifier stage for an ISFET biosensor has been developed. One chip integration of the newly developed signal process circuit, ISFETs and a Pt quasi-reference electrode has been carried out according to modified LOCOS p-well CMOS process. The fabricated chip showed gains of 0.8 and 1.6, good liniarity in the input-output relationship and very small power dissipation, 4mW. The chip was applied to realize a urea sensor by forming an immobilized urease membrane, using lift-off technique. on the gate of an ISFET. The urea sensor chip showed stable responses in a wide range of urea concentrations.

• 오토저널
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• 제15권3호
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• pp.89-95
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• 1993

This paper presents the development of CAD system for the design of lens of the Turn Signal Lamp that can model and simulate its optical performance. The system consists of three main modules: skin surface modeling module, inner lens modeling module and optical performance simulation module. Skin surface geometry can be modeled by the input of data file and inner lens can be modeled by the input of only four parameter using its geometric characteristics. Also light distribution pattern, the barometer of optical performance is generated by means of finite ray tracing method. The system display modeled geometry, ray tracing and generated light distribution pattern.

• 소음진동
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• 제4권3호
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• pp.307-318
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• 1994

Existence of any nonlinearity in responses of a nonlinear system is tested using a kurtosis or a fourth moment which has been widely used to characterize signal patterns. By inputting a harmonic signal to a system and investigating the distortions of an output signal from a harmonic pattern, which are due to violations of proportionality between the input and the output, it is judged whether the output is generated from a nonlinear system or not. Through applying the method presented in this work to simulation studies on detections of nonlinearities of a single degree of freedom system, in which three kinds of nonlinearities are treated as restoring force terms, feasibilities of the method are shown and the range of both frequency and input amplitude, in which the system generates nonlinear responses, is determined.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1992년도 학술논문발표회 논문집 제11권 1호
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• pp.29-32
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• 1992

In this paper, a systolic array structure is derived from the realization of 2-D IIR digital filters directed from the SFG(signal flow graph). After realized the 1-D formed partial systolic array, we implemented the complete systolic array to be cascaded 1-D form. The cascading of partial systolic arrays reduce the storage element which sued to delay input signal. 1-D systolic array is derived from that DG is designed through local communication approach and then it mapping to SFG. The derived structure is very simple and has high throughput because during new imput sample is supplied, new output is obtained every sampling period. And broadcast input signal is eliminated. Since the systolic array has property of regularity, modularity, local interconnection and highly synchronized multiprocessing, thus is very suitable for VLSI implementation.

• Journal of Power Electronics
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• 제10권3호
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• pp.306-312
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• 2010

In this paper, the design of an optimum single input Fuzzy controller for application in dc to ac converters is presented. Contrary to conventional Fuzzy controllers, the proposed controller has a smaller number of rules and tuning parameters but is capable of performing identically to a conventional controller. These benefits lead to a simpler controller design. The controller is designed as a PI controller for small-signal disturbances. However, for optimum large-signal performance, heuristic tuning is used. The tuning is less complicated and hence optimum large-signal performance is achievable. The system is simulated and a hardware prototype was developed for comparison purposes.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.142-145
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• 2001

In the double-talk situation where both the near-end and far-end signal present, the performance of echo cancellation using the NLMS algorithm is degraded easily since it freezes the adaptation in this situation. To solve this problem, which utilize the correlation function values of input signal instead of the input signal itself, have been proposed. Because this algorithm could be used to adapt the filter's parameters continuously even in the double-talk situation, give good convergence property compared with the NLMS. In this paper, we compare and analyze its performance. The computer simulation was performed and the results showed as that ECLMS algorithms were robust and kept the desirable performance even in the double-talk situation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.152-155
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• 2000

Oversampling modulators based on high-order sigma-delta modulation provide an effective means of achieving high-resolution A/D conversion in a VLSI technology. Because high-order noise shaping great]y reduces the quantization noise in the signal band. This paper introduces a third-order cascaded sigma-delta modulator that is stable for large input level. Modulator was simulated 3.3V single power supply voltage in 0.65$\mu\textrm{m}$ CMOS technology. It achieves 80㏈ SNR for a 20㎑ input signal bandwidth. A lock frequency is 3㎒ that is 80 oversampling ratio.

• 대한전자공학회논문지
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• 제8권4호
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• pp.7-16
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• 1971

쌍트란지스터 회로에 의하면 전류제어형의 부성저항소자가 가능하다. 이와같은 부성소자를 사용한 구형파발진회로의 바이어스전류에 신호파를 중첩함으로써 펄스폭변조회로를 구성하였다. 신호파가 정인 경우에는 한쪽의 트란지스터의 바이어스전류만을 증가시키고, 또 신호파가 부인 경우에는 다른 한쪽의 바이러스만을 증가시키는 방법을 채택하였다. 따라서 신호회로로서 일종의 전파정류회로의 변형을 채용하였다. 발진주기의 이론적해석과 회로정수결정의 설계지침을 구명하고 실험회로를 제시하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• 한국광학회지
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• 제5권2호
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• pp.291-297
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• 1994

Erbium첨가 광섬유 증폭기에서 증폭된 자연방출광(ASE) 출력의 일부를 대역투과 파장 필터를 거쳐 입력단으로 루프 귀환시켜 광증폭기를 특정 파장에서 발진시킴으로써 신호광에 대한 증폭 이득을 일정치에 고정시켰다. 증폭 이득과 ASE 출력 스펙트럼은 광증폭기가 발진하는한 입력광 power나 펌프광 power의 변화에 대하여 무관하였으며 귀환 루프의 손실에만 의존하였다. 또한 광증폭기에 저속으로 변조된 대신호가 입사하는 경우에도 이득포화에 의한 파형 왜곡없이 증폭이 가능하였다.